Verification Academy
Constraint random variable
SystemVerilog
rand-and-randc
,
SystemVerilog
,
byte-signed-within-range
basilleaf
July 6, 2022, 1:54am
3
In reply to
Shashank Gurijala
:
Hi,
May i know why its define as
32’h1
and not
4’h1
?
Since its a data array, it shouldnt be define as
data = '{32’h1}
?
show post in topic