In reply to ben@SystemVerilog.us:
Hi,
function bit[7:0] incr (logic [7:0]fll_out_bits ,logic [7:0] sar_mask, logic [8:0]mon_clk_count, logic [8:0]counts);
//INCR
begin
$display ("time %t ,INCR: , fll_out_bits= %b , mon_clk_count = %d, counts= %d, sar_mask = %d ", $time, fll_out_bits, mon_clk_count, counts, sar_mask);
fll_out_bits = fll_out_bits | (sar_mask >>1);
$display ("time %t ,INCR: , fll_out_bits= %b , " , $time, fll_out_bits );
return fll_out_bits ;
end
endfunction
function bit[7:0] decr (logic [7:0]fll_out_bits ,logic [7:0] sar_mask, logic [8:0]mon_clk_count, logic [8:0]counts);
begin
$display ("time %t ,DECR: , fll_out_bits= %b , mon_clk_count = %d, counts= %d, sar_mask = %d ", $time, fll_out_bits, mon_clk_count, counts, sar_mask);
fll_out_bits = (fll_out_bits & !(sar_mask)) | (sar_mask >> 1);
$display ("time %t ,DECR: , fll_out_bits= %b , " , $time, fll_out_bits );
return fll_out_bits ;
end
endfunction
property out_bits_incr_prpty;
bit v;
@(posedge monclk_output) disable iff (!i_en_fll)
$rose (sampled_monclk) |-> ((monclk_count < i_count), v=incr(o_prog_out_fll, sar_mask ,monclk_count, i_count) , $display ( "time %d FUNC VALUE value of incr =%d", $time, v)) ;
endproperty
property out_bits_decr_prpty;
bit v;
@(posedge monclk_output) disable iff (!i_en_fll)
$rose (sampled_monclk) |-> ((monclk_count >= i_count), v=decr(o_prog_out_fll, sar_mask ,monclk_count, i_count) , $display ( "time = %d,FUNC VALUE value of decr =%d", $time,v)) ;
endproperty
function is being called 1st time at 1417 (which is posedge of sampled monclk) but i am getting message from inside function at 0 time onwards. and why its printing INCR and DECR both at the same time from both the function since i am calling function at different condition.
time = 1417,FUNC VALUE value of decr =0
My intention function should get called only posedage of sampled_output and when sampled monclk goes 0
output :
time 0.000 ns ,INCR: , fll_out_bits= 10010000 , mon_clk_count = 0, counts= 256, sar_mask = 128
time 0.000 ns ,INCR: , fll_out_bits= 11010000 ,
time 0.000 ns ,DECR: , fll_out_bits= 10010000 , mon_clk_count = 0, counts= 256, sar_mask = 128
time 0.000 ns ,DECR: , fll_out_bits= 01000000 ,
time 2.000 ns ,INCR: , fll_out_bits= 10010000 , mon_clk_count = 0, counts= 256, sar_mask = 128
time 2.000 ns ,INCR: , fll_out_bits= 11010000 ,
time 32.000 ns ,DECR: , fll_out_bits= 10000000 , mon_clk_count = 0, counts= 256, sar_mask = 128
time 32.000 ns ,DECR: , fll_out_bits= 01000000 ,
time 32.000 ns ,INCR: , fll_out_bits= 10000000 , mon_clk_count = 0, counts= 256, sar_mask = 128
time 32.000 ns ,INCR: , fll_out_bits= 11000000 ,
time 134.000 ns ,DECR: , fll_out_bits= 10000000 , mon_clk_count = 1, counts= 256, sar_mask = 128
time 134.000 ns ,DECR: , fll_out_bits= 01000000 ,
time 134.000 ns ,INCR: , fll_out_bits= 10000000 , mon_clk_count = 1, counts= 256, sar_mask = 128
time 134.000 ns ,INCR: , fll_out_bits= 11000000 ,
time 137.000 ns ,DECR: , fll_out_bits= 10000000 , mon_clk_count = 2, counts= 256, sar_mask = 128
time 137.000 ns ,DECR: , fll_out_bits= 01000000 ,
time 137.000 ns ,INCR: , fll_out_bits= 10000000 , mon_clk_count = 2, counts= 256, sar_mask = 128
time 137.000 ns ,INCR: , fll_out_bits= 11000000 ,
time 140.000 ns ,DECR: , fll_out_bits= 10000000 , mon_clk_count = 3, counts= 256, sar_mask = 128
BUT FUNCTION is being called at 1417
time = 1417,FUNC VALUE value of decr =0
$rose (sampled_monclk) |-> ((monclk_count < i_count), v=incr(o_prog_out_fll, sar_mask ,monclk_count, i_count) , $display ( "time %d FUNC VALUE value of incr =%d", $time, v)) ;
|
xmsim: *E,ASRTST (time 1416500 PS) Assertion top.dut.u_assert_ip.AP_OUT_BITS_INCR_PRPTY has failed (1 cycles, starting 1416500 PS)
time 1417.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 0, counts= 256, sar_mask = 64
time 1417.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 1417.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 0, counts= 256, sar_mask = 64
time 1417.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 1417.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 0, counts= 256, sar_mask = 64
time 1417.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 1417.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 0, counts= 256, sar_mask = 64
time 1417.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 1422.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 0, counts= 256, sar_mask = 64
time 1422.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 2697.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 1, counts= 256, sar_mask = 64
time 2697.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 2697.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 1, counts= 256, sar_mask = 64
time 2697.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 2701.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 2, counts= 256, sar_mask = 64
time 2701.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 2701.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 2, counts= 256, sar_mask = 64
time 2701.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 2705.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 3, counts= 256, sar_mask = 64
time 2705.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 2705.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 3, counts= 256, sar_mask = 64
time 2705.000 ns ,INCR: , fll_out_bits= 01100000 ,
time 2709.000 ns ,DECR: , fll_out_bits= 01000000 , mon_clk_count = 4, counts= 256, sar_mask = 64
time 2709.000 ns ,DECR: , fll_out_bits= 00100000 ,
time 2709.000 ns ,INCR: , fll_out_bits= 01000000 , mon_clk_count = 4, counts= 256, sar_mask = 64
time 2709.000 ns ,INCR: , fll_out_bits= 01100000 ,
Could anyone see any thinf wrong ?