Harry Foster, Mentor Graphics
This special Verification Academy DAC session presents a historical perspective of functional verification—from transistors to systems. And then discusses a new era in functional verification with the emergence of functional verification solutions that address today's unique SoC challenges.
Tom Fitzpatrick, Mentor Graphics
You may have heard there's a new version of UVM that's recently been released. This session will teach you everything you need to know about the future of UVM. We'll briefly cover the new features included in UVM1.2 and how to minimize their impact, and we'll identify the key subset of UVM features that will make your environment truly reusable from block to system-level verification while providing the ideal platform for integrating new solutions and standards.
Rich Edelman, Mentor Graphics
"Old school" debug typically involves applying vectors directly to the design, a level of self-checking and then exploring the design with source, waves, and others to figure out what went wrong. With "new school" verification methodologies (UVM, randomization, golden reference models) the debug techniques need to be expanded. This session covers how you use the best of both worlds to find problems faster and to better answer "if you are done yet".
Stephen Bailey, Mentor Graphics
A key challenge in using FPGA prototypes is debugging, specifically in hardware or the interaction of software and hardware. Although many organizations have developed homegrown hardware instruments, silicon debug visibility continues to challenge the productive use of FPGA prototypes as a verification engine. Debugging system-level interactions driven by software sequences requires the ability to capture traces over a long period of time.This sessions discusses a solution that combines resource-efficient embedded instruments that dramatically increase visibility with software to provide a very flexible, easy-to-use silicon debug solution.
Matthew Ballance, Mentor Graphics
Verification productivity and reuse are of key concern when verifying today's complex designs. The ability to rapidly create large amounts of comprehensive test sequences at block, subsystem, SoC and system level are key to ensuring design quality. One key obstacle to achieving comprehensive testing today is the lack of a consistent stimulus specification that is reusable from block to system level. Recently, in response to industry demand, the Accellera Systems Initiative board launched a proposed working group to investigate whether to standardize a portable stimulus specification. This session will show how a portable stimulus specification brings 10-100x faster coverage closure to block level verification, and reusable comprehensive tests to SoC and system level verification.
Mark Eslinger, Mentor Graphics
Formal apps improve design quality and shorten the schedule for dealing with specific bottlenecks that occur during the verification process. In this session, we will discuss two of the most widely used apps in detail: connectivity verification and control and status register (CSR) verification. Come find out all you ever wanted to know about these apps, from someone who's "been there, done that"!
Jeremy Levitt, Mentor Graphics
What are formal property checking engines and how do they work? Why are they incredibly powerful for some properties, but not so good for others? What's the state of the art and what's coming in the near future? In this talk, we'll review the fundamentals as well as the recent breakthroughs that are driving advances in performance and capacity. Join us to instantly become a formal expert!
William Orme - ARM, Mark Olen & Jason Polychronopoulos - Mentor Graphics
The complexity and size of fabrics based on AMBA® 5 CHI present new verification challenges. This presentation from ARM and Mentor Graphics gives a brief introduction to the CHI protocol and then describes how a verification flow based on Mentor's CHI VIP, emulation operating system, hardware debugger and software debugger can be used to verify caches and fabrics that use this AMBA 5 protocol.
Alan Hunter - ARM
Developing and maintaining an effective and efficient verification suite for a complex system requires the ability to measure, understand, and improve the environment. Distributed, hierarchical caches are an example of interacting components within an SoC. Understanding how well the components are verified is a challenge since the cache interactions are complex, the components are distributed across an environment, and the data is spread across one or more regressions. This session discusses the challenges of collecting metrics, providing the visualization to understand complex state machine interactions, and then reviews results of a regression analysis.
Cliff Cummings - Sunburst Design
Fundamental questions most novice UVM users ponder include: Why uses classes instead of structs to define transactions for verification environments? What are advantages of using classes to represent transactions in a verification environment? Do I have to define different input and output classes for UVM testbenches? Why do I have to use do_methods() or field macros to override standard transaction methods? Why don't I just override the transaction methods directly? How do do_methods() and field macros work? SystemVerilog Guru and UVM expert, Cliff Cummings, will answer these questions and more to clarify many important details about UVM transactions.
Vigyan Singhal - Oski
Formal sign-off is a relatively new concept in the industry. Like simulation sign-off, it requires a thorough and systematic methodology. This includes: end-to-end checkers, constraints, abstraction models and coverage points. This talk discusses each component of the formal sign-off methodology so that formal can be applied in the verification sign-off flow to maximize efficiency & productivity.
Anand Iyer - Calypto Design Systems
Because over 80% of the final SoC/IP power is decided at the RT level, designers need to explore multiple power intent options and converge on power goals prior to place and route. This presentation will discuss how Questa-Power Aware and Calypto PowerPro enables users to accurately analyze various power intent choices and then optimize for best power reduction at RTL without losing any functionality.
Romain Tourneau - PLDA
The presentation will highlight how PLDA, built a PCIe UVM/SystemVerilog-based verification environment and how the work reduced time spent on verification by a factor of two compared to PLDA's previous Verilog/SystemVerilog-based environment.
Anupam Bakshi - Agnisys
UVM standard is non-binding. There are hundreds of guidelines that verification engineers must follow. Remembering these guidelines and adhering to them may not always be possible especially for novice users or large teams. Often even experts have to spend precious time tracing non-conformance to the standard.
Presenting DVinsight which is a free tool created by Agnisys to alleviate this time consuming and error prone yet necessary task. It's a smart editor with a special SV/UVM linter built in. As the user types in code it is checked for UVM conformance. Not only it saves time but it also produces correct by construction code reducing the time for debug.
Download all sessions in a single zip file.
