Verification Horizons
Exercising State Machines with Command Sequences
Creating Tests the PSS Way in SystemVerilog
Auto-Generating Implementation-Level Sequences for PSS
Selecting a Portable Stimulus Application Focal Point
Building a Better Virtual Sequence with Portable Stimulus
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Make Your Constraints More Dynamic with Portable Stimulus
Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus
Smoothing the Path to Software-Driven Verification with Portable Stimulus
Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow
Automating Tests with Portable Stimulus from IP to SoC Level
Bridging UVM to the Portable Stimulus Standard with Questa® inFact
Improving Performance and Verification of a System Through an Intelligent Testbench
Saving Time and Improving Quality with a Specification to Realization Flow
A New Stimulus Model for CPU Instruction Sets
Intelligent Testbench Automation with UVM and Questa®
Portable VHDL Testbench Automation with Intelligent Testbench Automation
Software-Driven Testing of AXI Bus in a Dual Core ARM® System
Power Up Hardware/Software Verification Productivity
Is Intelligent Testbench Automation For You?
Automated Generation of Functional Coverage Metrics for Input Stimulus
Targeting Internal-State Scenarios in an Uncertain World
Technical Papers
Results Checking Strategies with Portable Stimulus
Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
Managing and Automating HW/SW Tests from IP to SoC
Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
Verification Horizons BLOG
Portable Stimulus: Are you Ready for a Verification Revolution
Portable Stimulus and the Prius Model of New Technology Adoption
Taking the First Step in Portable Stimulus Adoption
Cats != Coverage
It Don’t Mean a Thing … Without Methodology
Better Virtual Sequences with Portable Stimulus
Prospecting for Reusable Assets with Portable Stimulus
Applying Portable Stimulus at DAC
Portable Test – Portable Intent, Portable Realization, or Both?
Developing Tests in Reverse with Portable Stimulus
Verification Academy Live Seminar: Portable Stimulus
Test Intent, Test Realization, and Separation of Concerns
Portable Stimulus Specification Released for Public Review
Reusing Existing Descriptions with New Languages
DAC 54 Spotlight on "Portable Stimulus"
Portable Stimulus: Standard vs. Tool vs. Language
Portable Stimulus the Hot Topic at DVCon U.S. '17
DVCon U.S. 2017: Bigger and Better!
DVCon India 2016–Outstanding Program Awaits
Portable Stimulus Takes an Important Step Forward
Portable Stimulus Taking Center Stage at DAC
Standards, Partners and Industry Collaboration Update
Portable Stimulus Applications at DVCon 2016
Modeling CPU Instruction Sets with a Portable Stimulus Specification
Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker