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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Portable Stimulus Basics

Portable Stimulus Basics

Portable Stimulus Basics Course | Subject Matter Expert - Tom Fitzpatrick | Coverage Topic

The new Portable Test and Stimulus Standard from Accellera provides the next leap in verification productivity needed to support the verification of our ever-growing system-on-chip (SoC) designs. In addition to increased complexity, SoC verification requires multiple platforms, including simulation, emulation and FPGA prototyping, each of which typically use different languages and formats for specifying the test, wasting precious time recreating the same test information throughout a project. Portable Stimulus addresses this problem by providing a single specification of test intent and coverage at a higher level of abstraction, allowing tools to generate target-specific implementations of the test for the desired platforms and freeing up the verification team to focus on what should be tested. In addition, Portable Stimulus also raises the level at which randomization can be applied, allowing many different but compatible scenarios to be generated from a single graph-based specification of test intent.

This Verification Academy course will provide an introduction to the new Portable Test and Stimulus Standard, starting with a discussion of the need for and goals of the standard, taking the viewer through the actual standard itself to provide an understanding of how to create your own specification of Portable Stimulus and then showing how a tool can generate UVM, C or other implementations of the test for your required platform. We close by showing how you can get started today by importing your existing UVM code into Portable Stimulus.


Tom Fitzpatrick
Portable Test and Stimulus
Walk

Sessions

Why Portable Stimulus?

Why Portable Stimulus? Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will discuss the motivation and goals for Portable Stimulus, explore the idea of scenario-level stimulus and examine the requirements for a viable Portable Stimulus solution.

Concepts & Language Introduction

Concepts & Language Introduction Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will provide a detailed understanding of what a scenario-level test actually involves; how to think and plan at the scenario level; and how to use the constructs in the Portable Test and Stimulus Standard to describe a scenario-level test.

Test Realization

Test Realization Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will walk you through the steps of how to define target-platform implementations for the elements of a Portable Stimulus model and how a Portable Stimulus tool can assemble these elements into a functional test on the target platform.

Importing UVM into Portable Stimulus

Importing UVM into Portable Stimulus Session | Subject Matter Expert - Tom Fitzpatrick | Portable Stimulus Basics Course

This session will show how to take advantage of Portable Stimulus automation to augment your existing UVM environment. You will learn how a Portable Stimulus tool like Questa® inFact can import transactions and functional coverage to generate more efficient scenario-level tests guaranteed to reach your coverage goals and how to easily integrate this automation into your regression environment.

Japanese Translations

Sessions include:

  • Why Portable Stimulus?
  • Concepts & Language Introduction
  • Test Realization
  • Importing UVM into Portable Stimulus

Verification Horizons

Designing A Portable Stimulus Reuse Strategy

Exercising State Machines with Command Sequences

Creating Tests the PSS Way in SystemVerilog

Auto-Generating Implementation-Level Sequences for PSS

Selecting a Portable Stimulus Application Focal Point

Building a Better Virtual Sequence with Portable Stimulus

Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

Make Your Constraints More Dynamic with Portable Stimulus

Getting Generic with Test Intent: Separating Test Intent from Design Details with Portable Stimulus

Smoothing the Path to Software-Driven Verification with Portable Stimulus

Portable Stimulus Modeling in a High-Level Synthesis User's Verification Flow

Automating Tests with Portable Stimulus from IP to SoC Level

Bridging UVM to the Portable Stimulus Standard with Questa® inFact

Improving Performance and Verification of a System Through an Intelligent Testbench

Saving Time and Improving Quality with a Specification to Realization Flow

A New Stimulus Model for CPU Instruction Sets

Intelligent Testbench Automation with UVM and Questa®

Portable VHDL Testbench Automation with Intelligent Testbench Automation

Software-Driven Testing of AXI Bus in a Dual Core ARM® System

Power Up Hardware/Software Verification Productivity

Is Intelligent Testbench Automation For You?

Automated Generation of Functional Coverage Metrics for Input Stimulus

Targeting Internal-State Scenarios in an Uncertain World

Technical Papers

Results Checking Strategies with Portable Stimulus

Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy

Managing and Automating HW/SW Tests from IP to SoC

Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Tackling Random Blind Spots with Strategy-Driven Stimulus Generation

UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Verification Horizons BLOG

Portable Stimulus: Are you Ready for a Verification Revolution
Portable Stimulus and the Prius Model of New Technology Adoption
Taking the First Step in Portable Stimulus Adoption
Cats != Coverage
It Don’t Mean a Thing … Without Methodology
Better Virtual Sequences with Portable Stimulus
Prospecting for Reusable Assets with Portable Stimulus
Applying Portable Stimulus at DAC
Portable Test – Portable Intent, Portable Realization, or Both?
Developing Tests in Reverse with Portable Stimulus
Verification Academy Live Seminar: Portable Stimulus
Test Intent, Test Realization, and Separation of Concerns
Portable Stimulus Specification Released for Public Review
Reusing Existing Descriptions with New Languages
DAC 54 Spotlight on "Portable Stimulus"
Portable Stimulus: Standard vs. Tool vs. Language
Portable Stimulus the Hot Topic at DVCon U.S. '17
DVCon U.S. 2017: Bigger and Better!
DVCon India 2016–Outstanding Program Awaits
Portable Stimulus Takes an Important Step Forward
Portable Stimulus Taking Center Stage at DAC
Standards, Partners and Industry Collaboration Update
Portable Stimulus Applications at DVCon 2016
Modeling CPU Instruction Sets with a Portable Stimulus Specification
Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker

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