Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few. Like simulation, formal has metrics which can be used to determine when verification on a design block is complete. In one session we’ll compare simulation metrics to formal metrics and how the two can be combined as part of an overall verification flow leveraging the UCDB database and Verification Management analysis and tracking. Next, you will see how proof coverage can be used beyond the traditional coverage closure methods to improve your verification results. One session will focus on how proof coverage can be used to help debug vacuous assertions and uncoverable cover statements. Another session will focus on how proof coverage can be used to help debug inconclusive properties and some simple steps you can take based on this information. The final session will cover 2 important topics regarding formal coverage having to do with reachability, which can help with bounded proofs, along with over constraint analysis which is an important part of an assurance driven formal flow.
