Search form

Main menu

My Account Menu

Evolving FPGA Verification Capabilities

Evolving FPGA Verification Capabilities Course | Subject Matter Expert - Ray Salemi | Simulation-Based Techniques Topic

Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone. The change in FPGA capabilities has results in the emergence of advanced FPGA system-on-chip (SoC) solutions, which includes the integration of third-party IP, DSPs, and multiple microprocessors—all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address. This course introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

This Verification Academy course is intended to be highly interactive—allowing the attendee to ask detailed questions concerning developing a successful FPGA verification methodology.

You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses.


Sessions

Introduction from Harry Foster

Introduction from Harry Foster Session | Subject Matter Expert - Harry Foster | Evolving FPGA Verification Capabilities Course

This session is an introduction to various code coverage metrics and how to apply them.

Overview and Welcome

Overview and Welcome Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session is an introduction to the seven steps for evolving your FPGA verification capabilities.

Code Coverage

Code Coverage Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session is an introduction to various code coverage metrics and how to apply them.

Test Planning

Test Planning Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session shows how to create a test plan that systematically captures all the functionality in your design.

Applied Assertions

Applied Assertions Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.

Transactions

Transactions Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session shows you how to create a transaction level test bench using modules instead of object.

Self-Checking Testbenches

Self-Checking Testbenches Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session demonstrates how to combine predictors and comparators to form a self-checking testbench.

Automatic Stimulus

Automatic Stimulus Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session introduces constrained-random stimulus for automatic stimulus generation.

Functional Coverage

Functional Coverage Session | Subject Matter Expert - Ray Salemi | Evolving FPGA Verification Capabilities Course

This session shows you how to implement functional coverage using SystemVerilog covergroups.