Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone. The change in FPGA capabilities has results in the emergence of advanced FPGA system-on-chip (SoC) solutions, which includes the integration of third-party IP, DSPs, and multiple microprocessors—all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address. This course introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
This Verification Academy course is intended to be highly interactive—allowing the attendee to ask detailed questions concerning developing a successful FPGA verification methodology.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses.
Learn more about Mentor Graphics Verification Services.