SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.
This 5-part Verification Academy course establishes the case for unit testing design and testbench code with SVUnit. It goes on to demonstrate unit testing of modules and classes (including UVM components) through code demos and commentary. The course finishes with case studies that show the quality benefits developers can expect from unit testing with SVUnit.
