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An Introduction to Unit Testing with SVUnit

SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is the only SystemVerilog test framework suited for both design and verification engineers.

  • SystemVerilog

Neil Johnson

Last Updated Feb 2016
  • ASIC
  • Components
  • FPGA
  • Open Source
  • SystemVerilog
  • Testbench
  • Unit Testing
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  • An Introduction to Unit Testing with SVUnit
  • 1. The Downside of Advanced Verification
  • 2. Introduction to SVUnit
  • 3. Your First Unit Test!
  • 4. Unit Testing UVM Components
  • 5. SVUnit Case Studies & Summary
  • Sessions

    • The Downside of Advanced Verification

      After more than a decade, it’s become obvious the advanced verification techniques we rely on, like constrained random verification, have fallen short of their potential.

      Track Feb 22, 2016 by Neil Johnson

      • SystemVerilog

    • Introduction to SVUnit

      A history of SVUnit and how it helps to directly address the poor code quality and code debug (redo) currently plaguing semiconductor teams.

      Track Feb 22, 2016 by Neil Johnson

      • SystemVerilog

    • Your First Unit Test!

      See how easy it is to get started with SVUnit. Generate a unit test template, write unit tests and run them all in less than 20 minutes!

      Track Feb 22, 2016 by Neil Johnson

      • SystemVerilog

    • Unit Testing UVM Components

      The ability to test UVM components is a key feature of SVUnit. We’ll generate a UVM specific unit test template, add some TLM connectivity and write a unit test to verify a simple UVM model.

      Track Feb 22, 2016 by Neil Johnson

      • SystemVerilog

    • SVUnit Case Studies & Summary

      SVUnit is being used by design and verification engineers to improve bug rates and write high quality code. We’ll look at case studies that support the use of SVUnit and summarize the case for unit testing.

      Track Feb 22, 2016 by Neil Johnson

      • SystemVerilog

  • Overview

    SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

    This 5-part track establishes the case for unit testing design and testbench code with SVUnit. It goes on to demonstrate unit testing of modules and classes (including UVM components) through code demos and commentary. The course finishes with case studies that show the quality benefits developers can expect from unit testing with SVUnit.

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