UVM Sequences

In testbenches written in traditional HDLs like Verilog and VHDL, stimulus is generated by layers of sub-routine calls which either execute time consuming methods (i.e. Verilog tasks or VHDL processes or procedures) or call non-time consuming methods (i.e. functions) to manipulate or generate data.

UVM - Universal Verification Methodology

Verification Methodology Team

Last Updated Mar 2018

This content is reserved for members. Register new account or login to view.

Full-access members only

Register your account to view UVM Sequences

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.