Mentor Verification IP
The verification components in the Mentor Verification IP library fit any verification environment. By facilitating and enhancing the application of transaction-level modeling (TLM), advanced SystemVerilog testbench features (such as constrained random testing), modern verification methodologies (such as OVM and UVM), and seamlessly integrating with other Mentor tools (such as Questa Verification Management, Questa Questa inFact and Veloce), Mentor Verification IP increases productivity even further.
Mentor Verification IP delivers a common interface across the library of protocols. This results in a scalable verification solution for popular protocols and standard interfaces, including stimulus generation, reference checking, and coverage measurements that can be used for RTL, TLM, and system-level verification.
Verification with Mentor Verification IP is straight forward: simply instantiate it as a component in your testbench. The built-in capabilities of Mentor Verification IP automatically provides the entries for the coverage database so you have the metrics in place to track whether all necessary scenarios are covered.
Mentor Verification IP is also integrated with the Questa debug environment and makes use of the transaction viewing capability in Questa so that you can get both signal-level and transaction-level debugging capabilities.
