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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
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      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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      • Coverage Forum

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • Start Here - Patterns Library Overview
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      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
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      • Configuring a Test Environment
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      • Register Abstraction Layer
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      • UVM Connect - SV-SystemC interoperability
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      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
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      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Exploring Formal Coverage
      • Processor Customization
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      • Formal and the Next Normal
      • Formal Verification Made Easy
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    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings

    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
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      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
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      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
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  • Home
  • Cookbook
  • Coverage
  • APB3 Protocol Test Plan

Coverage/APB3 Protocol Test Plan

  • Coverage/APB3 Protocol Test Plan
    • Chapter Contents:
    • Coverage/Introduction
    • Coverage
      • Coverage Metrics and process (Theory).
    • Coverage/What is coverage
    • Coverage/Kinds of coverage
    • - Coverage/Code Coverage Metrics
    • - Coverage/Functional Coverage Metrics
    • Coverage/Specification to testplan
    • - Coverage/Executable Testplan Format
    • Coverage/Testplan to functional coverage
    • - Coverage/Design For Analysis
      • Coverage Examples (Practice).
    • Coverage/Bus Protocol Coverage
    • - Coverage/APB3 Protocol Test Plan
    • - Coverage/APB3 Protocol Monitor
    • Coverage/Block Level Functional Coverage Example
    • - Coverage/UART Example Test Plan
    • - Coverage/UART Example Covergroups
    • Coverage/Datapath Example
    • - Coverage/BiQuad IIR Filter Test Plan
    • - Coverage/BiQuad IIR Filter example covergroups
    • Coverage/System Level Functional Coverage Example
      • Appendices.
    • Coverage/Requirements Writing Guidelines
  • Glossary
      terms used:
    • Assertion
    • Coverage
    • Functional Coverage
    • Test
    • Test Plan
  • API Reference
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  • Page Links
    Pages which link to/from this page:
    • Coverage
    • Coverage/Bus Protocol Coverage

    • Coverage/
      APB3 Protocol Test Plan
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    • Download PDF:
      Coverage Cookbook
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Coverage: APB3 Protocol Test Plan

During the verification planning process a test plan should be created that lists the features of a design, how they are to be verified and how test closure will be achieved. The APB3 protocol monitor is a reusable verification component (VIP) and it can be reused when verifying any design which has an APB3 bus interface. The test plan that is listed below would be included as part of the test plan for such a design, effectively imported as a leaf in the test plan hierarchy.

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