Released on March 25th, 2021
UVM testbenches are powerful, reusable programs that generate transaction-level stimulus and analyze transaction-level results, leaving the signal-level control to bus functional models. One has to wonder why we are writing this complex software using a language intended to describe RTL in an event-driven simulator. Wouldn’t we be better off using the most popular software development language1, Python?
This session introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.