Verification takes many forms. What some consider to be a modern verification methodology may be of a scope that others are not able to support. Some implement a Portable Stimulus-enabled, constrained-random, coverage-driven methodology that utilizes emulation and prototyping to enable hardware-software co-development and accelerate system deployment. Others build an implementation of their FPGA and test.
Both extremes are borne of differing constraints. Both have been used successfully, and unsuccessfully, to deploy products to market. The goal of any verification process is to ensure that the design performs as intended, and not to “find bugs” or to “close coverage”. Of course, these are hurdles that must be addressed. Finding bugs is necessary because designs and test benches are never perfect. Closing coverage is necessary because it’s a metric by which we know how complete our stimulus is. Yet, while a verification effort that closed coverage and found no new bugs in days or weeks is more likely to see clean deployment, it is still not guaranteed any more than is a lab-tested implementation.
Why? Because most designs today are built across teams, across companies, across geographies, across languages and across time. At every boundary lies a gap. These gaps are fertile ground for bugs to thrive and go undetected. Current challenges: Very few designs today are flat. A hierarchical design consists of layers of functions. Gaps exist by definition between functions not designed together – across all combinations of the aforementioned boundaries.
This workshop will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.
