Browse all content in Siemens Verification Academy with the tag Low Power

March 2019

• Effective Elements List and Transitive Natures of UPF Commands

  Low Power Feb 28, 2019 pdf

February 2019

• Low Power Apps: Shaping the Future of Low Power Verification

  Low Power Feb 28, 2019 pdf

• Low Power Verification Forum

  Low Power Feb 05, 2019 Gordon Allan Webinar

January 2019

• Industry Advancements Required to Close the Power Management Verification Gap

  Low Power Jan 28, 2019 Sriram Hariharan Webinar

• Deploying A Metrics Driven Low Power Methodology for Your RTL IP

  Low Power Jan 28, 2019 Qazi Ahmed Webinar

• Low Power Verification & Analysis with Emulation

  Low Power Jan 28, 2019 Shantanu Samant Webinar

• Productive Low Power Debug Across All Engines and Flows

  Debug Jan 28, 2019 Gordon Allan Webinar

December 2018

• A New Approach to Low-Power Verification: Power Aware Apps

  Simulation & Emulation Dec 03, 2018 Verification Horizons Article

August 2018

• Power Aware Simplifies Parametric PA-SIM Regression

  Low Power Aug 02, 2018 pdf

June 2018

• Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs

  Low Power Jun 29, 2018 Progyna Khondkar Article

March 2018

• Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs

  Low Power Mar 07, 2018 Ellie Burns Webinar

• SATA Specification 3.3 Gaps Filled by SATA QVIP

  Verification IP Mar 01, 2018 Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens Eda Article

• From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1

  Low Power Mar 01, 2018 Progyna Khondkar Article

December 2017

• PA GLS: The Power Aware Gate-level Simulation

  Simulation & Emulation Dec 06, 2017 Progyna Khondkar Article

August 2017

• Low-Power Design using High-Level Synthesis for Automotive Image Sensor

  High-Level Synthesis Aug 07, 2017 pdf

February 2017

• Artifacts of Custom Checkers in Questa® Power Aware Dynamic Simulation

  Simulation & Emulation Feb 28, 2017 Verification Horizons Article

January 2017

• The Fundamental Power States for UPF Modeling and Power Aware Verification

  Standards Jan 04, 2017 Verification Methodology Team Article

• Is Your Power Aware Design Really X-Aware?

  Simulation & Emulation Jan 03, 2017 Verification Methodology Team Article

• Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification

  Standards Jan 03, 2017 Verification Methodology Team Article

November 2016

• Power Aware Libraries: Standardization and Requirements for Questa® Power Aware

  Simulation & Emulation Nov 14, 2016 Verification Horizons Article

September 2016

• Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

  UVM - Universal Verification Methodology Sep 09, 2016 Gordon Allan Webinar

August 2016

• Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts

  Clock-Domain Crossing Aug 26, 2016 Kurt Takara Paper

• Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts

  Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf

April 2016

• Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs

  Low Power Apr 13, 2016 Joe Hupcey pdf

March 2016

• Questa Visualizer - Power Aware Debug

  Debug Mar 18, 2016 Chuck Seeley Demo