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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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June 2017 - Volume 13 Issue 2 (2)

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March 2017 - Volume 13 Issue 1 (2)

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March 2016 - Volume 12 Issue 1 (1)

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October 2011

SystemC & TLM-2.0 Monitors and Talkers
Acceleration Oct 27, 2011 John Stickley Session

August 2011

Advanced Debug with Questa
Debug Aug 01, 2011 pdf

June 2011

Verification Horizons - Volume 7, Issue 2
Standards Jun 01, 2011 Tom Fitzpatrick pdf

April 2011

Transforming Verification and Verification Management
Verification Management Apr 08, 2011 Tom Fitzpatrick Webinar
Power Aware Verification & UPF Tricks
Low Power Apr 08, 2011 Tom Fitzpatrick Webinar

March 2011

Are OVM & UVM Macros Evil? A Cost-Benefit Analysis
UVM - Universal Verification Methodology Mar 08, 2011 Adam Erickson pdf

February 2011

CDC Verification
Clock-Domain Crossing Feb 25, 2011 Harry Foster Track
Overview and Welcome
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Introduction to CDC
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Understanding Metastability
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Metastability Verification Flow
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Modeling Metastability
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Integrating CDC Into A Flow
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
H/W-Assisted Testbench Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Testbench Acceleration Depicted
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Modeling for Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Testbench Acceleration Flow
Acceleration Feb 25, 2011 Hans Van Der Schoot Session
Why Plan?
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
Why It's Hard
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
Plan of Attack
Planning, Measurement and Analysis Feb 25, 2011 Peet James Session
SystemVerilog Concurrent Assertions
SystemVerilog Feb 25, 2011 Cliff Cummings Webinar
SystemVerilog Testbench Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Track
Introduction to the Verification Academy
Planning, Measurement and Analysis Feb 25, 2011 Harry Foster Session
Verification Planning and Management
Planning, Measurement and Analysis Feb 22, 2011 Peet James Track
Verification Horizons - Volume 7, Issue 1
Standards Feb 01, 2011 Tom Fitzpatrick pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Functional Safety Webinar

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

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