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Transforming AI with HBM: Siemens’ Avery VIP powers Rambus’ Industry-First HBM4 Memory Controller
Verification IP Sep 18, 2024 Vivek Kaliki - Siemens Eda link
Exploring Essential Concepts in Formal Verification
Formal Verification Sep 18, 2024 Nicolae Tusinschi link
MARLUG - 2024
FPGA Verification Sep 18, 2024 Austin Mam Seminar
Assertions and Benefits of Abstractions in Formal Verification
Formal Verification Sep 11, 2024 Nicolae Tusinschi link
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Formal Verification Sep 11, 2024 Nicolae Tusinschi Webinar
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Formal Verification Sep 11, 2024 Nicolae Tusinschi pdf
Understanding Formal Verification
Formal Verification Sep 05, 2024 Nicolae Tusinschi link
Jump-Start Your UVM Journey with UVM Framework (UVMF)
UVM Framework Sep 04, 2024 Dennis Brophy - Siemens Eda link

August 2024

The Future of Multi-Die System Verification with UCIe
Verification IP Aug 21, 2024 Justin Bunnell pdf
The Future of Multi-Die System Verification with UCIe
Verification IP Aug 21, 2024 Justin Bunnell Webinar
Advanced Analytics for Accelerating RDC Verification Closure
Reset-Domain Crossing Aug 13, 2024 Reetika - Siemens Eda link
Portable Stimulus and VIP: Like a Hand in a Glove
Verification IP Aug 08, 2024 Tom Fitzpatrick link
Announcing Avery UCIe 2.0 Verification IP from Siemens EDA
Verification IP Aug 06, 2024 Gordon Allan link
UVM Framework Release 2023.4_2
UVM Framework Aug 05, 2024 Bob Oden tar

July 2024

Verification Challenges and Solutions for Multi-Die Systems (UCIe)
Verification IP Jul 29, 2024 Vivek Kaliki - Siemens Eda link
Accelerating Verification of Computational Storage Designs (NVMe)
Verification IP Jul 29, 2024 Vivek Kaliki - Siemens Eda link
Accelerate Closure of Reset Path and Reset Domain Crossing Issues in Digital Designs
Reset-Domain Crossing Jul 24, 2024 Farhad Ahmed link
Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Simulation Jul 24, 2024 Fan Zhang Webinar
Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Simulation Jul 24, 2024 Fan Zhang pdf

June 2024

Questa CDC-FX: Metastability Effects Delay Modeling
Clock-Domain Crossing Jun 28, 2024 Kurt Takara Paper
Questa CDC-FX: Metastability Effects Delay Modeling
Clock-Domain Crossing Jun 28, 2024 Kurt Takara pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag va live 2025 - el segundo

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