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Show Less

May 2021

The Proper Care and Feeding of Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Layered Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Writing and Managing Tests
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Setting Up the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Using the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Register-Based Testing
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 pdf

April 2021

A Methodology for Comprehensive CDC+RDC Analysis
Clock-Domain Crossing Apr 20, 2021 Kurt Takara pdf

March 2021

Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda pdf
Making Your DPI-C Interface A Fast River Of Data
SystemVerilog Mar 31, 2021 Rich Edelman pdf
Handling Reset Domain Crossing for Designs with Set-Reset Flops
Reset-Domain Crossing Mar 31, 2021 Abdul Moyeen pdf
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar pdf
Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation
Low Power Mar 31, 2021 Abdul Moyeen pdf
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller pdf
Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing Mar 26, 2021 Ping Yeung pdf
Applying Big Data to Next-Generation Coverage Analysis and Closure
Verification Management Mar 26, 2021 Darron May pdf
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich pdf
Preventing Glitch Nightmares on CDC Paths: The Three Witches
Clock-Domain Crossing Mar 26, 2021 pdf
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi pdf
Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Ping Yeung pdf
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara pdf

February 2021

A Methodology for Comprehensive CDC Analysis
Clock-Domain Crossing Feb 26, 2021 Atul Sharma pdf
I Didn't Know Visualizer Could Do that
Debug Feb 05, 2021 Rich Edelman pdf
ISO 26262 Creating an Optimal Safety Architecture
Functional Safety Feb 02, 2021 Jacob Wiltgen pdf

December 2020

Mathworks Integration
UVM Framework Dec 29, 2020 Bob Oden pdf

User2User - Santa Clara

Tuesday, May 20th-8:00 AM PDT

Check out the User2User North America 2025 conference session catalog and plan the sessions you'll attend.

Productivity Webinar

Wednesday, May 21st-8:00 AM PDT

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Traceability Webinar

Wednesday, May 28th-8:00 AM PDT

Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author

Verification Academy Live

Tuesday, Jun 03rd-6:30 AM PDT

Hudson, MA | American Heritage Museum

Fault Simulation Webinar

Wednesday, Jun 04th-8:00 AM PDT

Enhancing Automotive Safety Verification Using Questa One Sim FX

Verification Academy Live

Thursday, Jun 05th-7:30 AM PDT

Huntsville, AL | Siemens Training Center

Coverage Webinar

Wednesday, Jun 18th-8:00 AM PDT

Accelerating Functional Coverage with Questa One CX

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