`define macros usage
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25
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114514
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December 16, 2015
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Generate unique elements in an array
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46
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65290
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February 21, 2019
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Fork within loop with join ALL
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35
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54808
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August 10, 2023
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Why do we need virtual interfaces in system verilog?
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24
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64930
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June 4, 2019
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What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example
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32
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53275
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August 8, 2021
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Checking clock period using system verilog assertion
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30
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51967
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April 5, 2024
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Need to Use Variable in Assertions ## Delay
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46
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32055
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July 1, 2021
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Confusion in fork join ... disable fork
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25
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40446
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July 24, 2021
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What difference between @event and wait (event.triggered)?
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14
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52443
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November 25, 2022
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Assert Property vs Cover Property
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19
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44704
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June 11, 2019
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Fork join_none inside for loop
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30
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34374
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June 28, 2022
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P_sequencer and m_sequencer
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11
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53524
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October 22, 2015
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How to access a DUT signal from a UVM test case class?
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21
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38498
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April 11, 2023
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Queue and mailbox
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13
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46256
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July 5, 2019
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SVA : using $past
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15
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39185
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October 28, 2020
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Creating new instances of a covergroup using an array
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27
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28937
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July 30, 2017
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Oring of ifdef
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9
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47513
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November 9, 2017
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Constraint randomization of an array
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20
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31973
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January 31, 2019
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Verification of ASYNCHRONOUS FIFO
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21
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28274
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February 18, 2022
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Constrain sum of elements in an array
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20
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27927
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May 22, 2023
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How to Terminate UVM simulation?
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23
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23996
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April 10, 2020
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P_sequencer / m_sequencer
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9
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36335
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September 22, 2020
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Range must be bounded by constant expressions
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11
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32650
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March 2, 2024
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Uvm_config_db usage a big confusion
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10
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33180
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November 20, 2018
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Why `ifndef and `define are used together?
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13
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29064
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July 26, 2019
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Fatal: (SIGSEGV) Bad handle or reference, Error
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22
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22091
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April 14, 2014
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Automatic variables in fork
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14
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26995
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February 9, 2022
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Assertion to check stability of a signal for 'n' clocks
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15
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25997
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January 29, 2022
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Regarding Method Overriding / Polymorphism SystemVerilog
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25
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20350
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August 7, 2018
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How to stop or kill the running sequences
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15
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24606
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December 3, 2017
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Calling of build phase?
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24
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19302
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February 29, 2024
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UVM_ERROR
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71
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11260
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December 15, 2017
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How to get array of coverpoints
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14
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21863
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February 19, 2021
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Interview Questions on Assertions
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20
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18440
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February 22, 2024
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Initializing a multidimensional associative array
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11
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24181
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October 21, 2020
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How to safely delete entries from a queue
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12
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23126
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May 26, 2017
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Calling task inside function
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12
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22193
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January 20, 2020
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Why system verilog does not allow always block in program scope?
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11
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22773
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May 19, 2016
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Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?
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9
|
24811
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April 13, 2015
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How to exit from simulation on getting UVM_ERROR
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12
|
21377
|
June 3, 2021
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Casting into an enum
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10
|
22887
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June 19, 2017
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What is the difference between modport and clocking block
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12
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20275
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June 17, 2021
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How to get virtual interface in sequence
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28
|
13502
|
February 18, 2017
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SVA: throughout vs until
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9
|
21747
|
March 14, 2020
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Randomizing a dynamic array size
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13
|
18227
|
December 2, 2018
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Conditional Statement in Assertion Property
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11
|
19362
|
May 18, 2018
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SV assertion for clock gating & Reset check
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22
|
13211
|
August 10, 2021
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Generating random values in increasing order
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16
|
15303
|
June 27, 2022
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A constraint to generate odd_even_odd....... etc sequence
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9
|
19822
|
June 9, 2017
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Coverpoint for an array or queue
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9
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19331
|
May 31, 2021
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