Why system verilog does not allow always block in program scope?

SystemVerilog
1

Can you please explain why only initial block is allowed in program scope ?

2

The program block came from the Vera verification language that was donated to SystemVerilog. In Vera, a program was a single procedure that represented the ā€œtestā€. Your test was started at time 0 and when the test terminated, the program terminated the simulation. If you needed multiple test threads, you either had to use the fork statement to start it, or use multiple programs. When the last program terminated, the simulation terminated.

As part of the integration with SystemVerilog, the program was turned into a module-like construct with ports and initial blocks are now used to start the test procedure. Because an always block never terminates, it was kept out of the program block so the concept of test termination would still be there.

Today, most people do not utilize this termination feature because the OVM/UVM have their own test termination mechanisms. The program block is no longer a necessary feature of the language other than to help people converting over from Vera to SystemVerilog.

See my blog: Are Program Blocks Necessary?

3

In reply to dave_59:

Thanks dave

4

In reply to vybhava:

Thanks Daveā€¦Good Explaination

5

In reply to akghona:

Hi,

Suppose if we use forever in program block, what will happen. what is the difference between always and forever.

I think this is very very basic doubt, But Please clarify this.

Thanks,
Karalamoorthy

6

In reply to karala.pandi:

For the most part, there is no behavioral difference between

always begin 
       @(posedge clk) $display("at the posedge of clk");
       end

and

initial begin 
          forever @(posedge clk) $display("at the posedge of clk");
       end

It is mainly a difference in intent. Some synthesis tools ignore all the code in an initial block thinking they are for simulation only and do not describe hardware to be synthesized.

Technically, there are a few thing you can do with a forever statement that you cannot do with an always block. As a looping statement, you can break out of a forever loop, and if you name the statement, you can disable it. So you can terminate the process created by an initial block. There is no way to terminate the process created by an always block.

7

In reply to dave_59:

Hi,

The $finish statement can be able to call in always block right, then why we cant terminate the process created by the always block as like initial/forever block.

8

In reply to cas_mems:

You can also terminate the always process by holding the power button down on your computer, but that wouldnā€™t be very graceful, would it? $finish will terminate all processes, not just the always block.

There are many different ways of describing the same behavior in any language, be it a computer language or human. But each way may have subtle differences that many not be understood by all readers. That is why I recommend limiting the number of constructs and ways that you represent certain behaviors that you use in SystemVerilog.

1 Like
9

In reply to dave_59:

Thanks Dave

10

In reply to cas_mems:

thanks Dave.

11

In reply to dave_59:

Why this program block has limitation on join_none/join_any

program test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endprogram

Output :
0 e
0 a
0 d

module test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endmodule

Output :
0 e
0 a
0 d
10 b
20 c

What could be the limitation in this program when making join_non/join_any

12

In reply to vamsi.int@gmail.com:

Read the paragraph labeled ā€˜3.ā€™ in my blog: Are Program Blocks Necessary?

1 Like
13

Hi Dave, I think the ages have decomposed the link to ā€œAre Program Blocks Necessary?ā€.
Iā€™m curious about the answer to vamsi.intā€™s example.
Why are there different outputs? i.e why does the module display b and c even after the process has been terminated at time 0?

14

program block automatically calls the $finish. If we use always block in the program, there is no point to use the always block. The main functionality of the always block is until unless we end the simulation, it should continue. But program block ends the always block . So, thatā€™s why system verilog does not allow always block in program scope.