Why system verilog does not allow always block in program scope?

In reply to cas_mems:

You can also terminate the always process by holding the power button down on your computer, but that wouldn’t be very graceful, would it? $finish will terminate all processes, not just the always block.

There are many different ways of describing the same behavior in any language, be it a computer language or human. But each way may have subtle differences that many not be understood by all readers. That is why I recommend limiting the number of constructs and ways that you represent certain behaviors that you use in SystemVerilog.

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