Why system verilog does not allow always block in program scope?

SystemVerilog
11

In reply to dave_59:

Why this program block has limitation on join_none/join_any

program test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endprogram

Output :
0 e
0 a
0 d

module test;
 initial 
   begin
     fork
       $display($time, " a");
       #10 $display($time, " b");
       #20 $display($time, " c");
       $display($time, " d");
     join_none
     $display($time, " e");
   end
endmodule

Output :
0 e
0 a
0 d
10 b
20 c

What could be the limitation in this program when making join_non/join_any