How to Terminate UVM simulation?

Hi Everyone,

   i have gone through the verious recommanded approches to teminate my uvm simulation but i have not find good solution. the simulation is not terminating.

approch 1:

a. i am raising and dropping objection in run_phase() of all components.
using phase.raise_objection(this) , phase.drop_objection(this)
b. in test class using phase.phase_done.display_objections();
c. above statement show all objections are dropped.
d. but my simulation has hanged at top module while clock generation.

approch 2:
along with approch 1 , i have called global_stop_request()/stop_request() function. But result, simulation did not terminate.

approch 3:
along with approch 1,2 , i have set_drain_time(), even status is same. i have not seen any differnce with seting drain time to 0 ,20 ,30 or any value.

How the Drain time will effect to terminate simulation.

approch 4:
i added following two staments at “task body()”/ pre_body(),post_body();

please give me guide line to stop simulation();


You should only raise_objection() and drop_objection() in the run_phase() of your tests, using the phase itself and not uvm_test_done (i.e. phase.raise_objection() and phase.drop_objection()). Do not use them in any components or sequences as it is difficult to track down any offenders as you are finding out. By using these in your tests, you will only have one outstanding objection per test.

Do not use global_stop_request() as this will not work in UVM.

Drain time is an additional amount of time that the run_phase() will execute after all objections are dropped. This can be set on a per-test basis to account for any additional processing time needed after all your test sequences have completed.

Use raise_objection and drop objection in test and environment run phase . May be your EOT is blocking the end of simulation some where please check for it.
Implement the watchdog timer and use UVM_TIMEOUT=3500_0ns.

In reply to cgales:

HI cgales ,

Thank you very much.

my top module is as follows :

module top;

  1. interface instance
  2. DUT instance and signal connection
  3. generating clock as follows

#10 clock = ~clock;


calling run_test();


The simulation is not terminating because the clock generation is running infinitely, so my test objection is not dropping.


The clock generation running infinitely is not an issue. When the UVM phasing mechanism reaches the end of all phases, a $finish will be called to terminate simulator execution, including the clock.

There must be something else that is preventing the UVM from finishing. If you set UVM_VERBOSITY to UVM_DEBUG, you should see messages as each UVM phase executes.

In reply to Chandra Bhushan Singh:

HI chandra ,

thank you.

i used uvm_timeout. it’s giving uvm_fatal error and terminating simuation. i think we can do this by printing some fatal error.


I think you are blocked in some where in wait statement in some logic or @. One think you can do don not use raise_objection and drop_objection in deep in hierarchical. Just use it in test and enviroment . And put your eot condition in env in run phase. When all sequences is completed test also drop the obection.

Can you post your test code if possible otherwise use stepping into your test code and check where it is blocking.

In reply to Chandra Bhushan Singh:

Hi chandra,

i put some display() statments at end of each phase , all messages are displayed.
i put only raise/drop objection in test. the raising is happening but not drop_objection();

Following message displaying :

The total objection count is 1


Source Total

Count Count Object


0 1 uvm_top

1 1 uvm_test_top


my last statements in test :



In reply to Chandra Bhushan Singh:

Hi chandra ,

in test ,

  1. fork
  2. starting slave seqr
  3. starting master seqr

the simulation is coming upto line number 5. but not executing line 6.

whenever i will comment line 3(i.e staring master seqr) my simulation is teminating. so i came to know there is problem in master sequencer. how to debug it . please guide me

very thanks

0.phase.drop_objection(this); i think it is typo or you doing it ??.
Can you make sure that test run phase should have only raise_objection and drop objection.
If its true then only one case it is blocked because of starting master.start() is not completing.

In reply to Chandra Bhushan Singh:

sorry that is phase.raise_objection(this). typing mistake.

In reply to kbkdec15:

why should we raise/drop_objection in test or env.

what happens if we raise/drop_objection is all run_phase();

is there any way to drop the objection which is not dropped.



If you raise objection in run phase of each component then it may be the case then some run phases are not completing, so that will block your end of simulation. For example your driver may be the thread which will never end. So your driver may hold the simulation. If you raise objection in env with eot condition done For example ( tx_msg == rx_msg) its mean you are holding simulation to complete your purpose. then drop the objection. In test you are waiting for completion of all sequences.

CB Singh

In reply to Chandra Bhushan Singh:

Hi chandra ,

Thank you.

last one , is there any way to drop the objection which is not dropped ?



I think this Sunburst paper is useful,take a look


In reply to Hash:

Hi hash ,

Thank you for reply.

i had gone through. Because of multiple concepts i got confused.


Hi kbkdec15
I am a beginner in UVM. I also faced the problem of non stopping simulation.
In my case I gave `timescale in my files. Then it worked. I don’t know whether it will work in your case.


In reply to rakhimittal:

hi rakhi

thanks for your reply.

i had done it,working well.

In reply to Balu_15:

How did you resolve this issue.
I am also facing the same issue, not able to terminate the UVM Simulation.
Please help.