How to Terminate UVM simulation?

hi,

If you raise objection in run phase of each component then it may be the case then some run phases are not completing, so that will block your end of simulation. For example your driver may be the thread which will never end. So your driver may hold the simulation. If you raise objection in env with eot condition done For example ( tx_msg == rx_msg) its mean you are holding simulation to complete your purpose. then drop the objection. In test you are waiting for completion of all sequences.

Thanks
CB Singh