How to Terminate UVM simulation?

UVM
,
4

In reply to cgales:

HI cgales ,

Thank you very much.

my top module is as follows :

module top;

  1. interface instance
  2. DUT instance and signal connection
  3. generating clock as follows

always
#10 clock = ~clock;

initial
begin

calling run_test();
end

endmodule

The simulation is not terminating because the clock generation is running infinitely, so my test objection is not dropping.

Thanks
kbkdec15

5

The clock generation running infinitely is not an issue. When the UVM phasing mechanism reaches the end of all phases, a $finish will be called to terminate simulator execution, including the clock.

There must be something else that is preventing the UVM from finishing. If you set UVM_VERBOSITY to UVM_DEBUG, you should see messages as each UVM phase executes.

6

In reply to Chandra Bhushan Singh:

HI chandra ,

thank you.

i used uvm_timeout. it’s giving uvm_fatal error and terminating simuation. i think we can do this by printing some fatal error.

Thanks
kbkdec15

7

I think you are blocked in some where in wait statement in some logic or @. One think you can do don not use raise_objection and drop_objection in deep in hierarchical. Just use it in test and enviroment . And put your eot condition in env in run phase. When all sequences is completed test also drop the obection.

8

Can you post your test code if possible otherwise use stepping into your test code and check where it is blocking.

9

In reply to Chandra Bhushan Singh:

Hi chandra,

i put some display() statments at end of each phase , all messages are displayed.
i put only raise/drop objection in test. the raising is happening but not drop_objection();

Following message displaying :

The total objection count is 1

---------------------------------------------------------

Source Total

Count Count Object

---------------------------------------------------------

0 1 uvm_top

1 1 uvm_test_top

---------------------------------------------------------

my last statements in test :

phase.phase_done.display_objections();
phase.drop_objection(this);
phase.phase_done.display_objections();

Thanks
kbkdec15

10

In reply to Chandra Bhushan Singh:

Hi chandra ,

in test ,
0.phase.drop_objection(this);

  1. fork
  2. starting slave seqr
  3. starting master seqr
    4.join
    5.phase.phase_done.display_objections();
    6.phase.drop_objection(this);
    7.phase.phase_done.display_objections();

the simulation is coming upto line number 5. but not executing line 6.

whenever i will comment line 3(i.e staring master seqr) my simulation is teminating. so i came to know there is problem in master sequencer. how to debug it . please guide me

very thanks
kbkdec15

11

0.phase.drop_objection(this); i think it is typo or you doing it ??.
Can you make sure that test run phase should have only raise_objection and drop objection.
If its true then only one case it is blocked because of starting master.start() is not completing.

12

In reply to Chandra Bhushan Singh:

sorry that is phase.raise_objection(this). typing mistake.

13

In reply to kbkdec15:

why should we raise/drop_objection in test or env.

what happens if we raise/drop_objection is all run_phase();

is there any way to drop the objection which is not dropped.

Thanks
kbkdec15

14

hi,

If you raise objection in run phase of each component then it may be the case then some run phases are not completing, so that will block your end of simulation. For example your driver may be the thread which will never end. So your driver may hold the simulation. If you raise objection in env with eot condition done For example ( tx_msg == rx_msg) its mean you are holding simulation to complete your purpose. then drop the objection. In test you are waiting for completion of all sequences.

Thanks
CB Singh

15

In reply to Chandra Bhushan Singh:

Hi chandra ,

Thank you.

last one , is there any way to drop the objection which is not dropped ?

Regards/Thanks
kbkdec15

16

Hi

I think this Sunburst paper is useful,take a look
http://www.sunburst-design.com/papers/CummingsDVCon2011_UVM_TerminationTechniques.pdf

-BR
Hash

17

In reply to Hash:

Hi hash ,

Thank you for reply.

i had gone through. Because of multiple concepts i got confused.

thanks
kbkdec15

18

Hi kbkdec15
I am a beginner in UVM. I also faced the problem of non stopping simulation.
In my case I gave `timescale in my files. Then it worked. I don’t know whether it will work in your case.

Rakhi

19

In reply to rakhimittal:

hi rakhi

thanks for your reply.

i had done it,working well.

20

In reply to Balu_15:

Hi,
How did you resolve this issue.
I am also facing the same issue, not able to terminate the UVM Simulation.
Please help.

21

In reply to ramesh.mr:

In reply to Balu_15:
Hi,
How did you resolve this issue.
I am also facing the same issue, not able to terminate the UVM Simulation.
Please help.

What kind of not stopping do you face? Please explain.

By the way to stop the simulation using UVM there is 1 meachanism. It is the objection mechanism. This is the default way to stop a simulation in the operational mode. And it has to be implemented. If there are no objections the simulation stucks at runtime 0.
If somethinh goes wrong in your simulation and the obejction mechanism does not work you have the option to set a timeout. This becomes active only in the error case.

22

In reply to chr_sue:

Thank you for replying.
This issue is resolved, after adding below code to uvm test

task delay_to_end(uvm_phase phase);
#1;
`uvm_info(get_name(),$sformatf(“Now to end %s…”,phase.get_name()),UVM_LOW)
phase.drop_objection(this);
endtask

function void phase_ready_to_end(uvm_phase phase);
    if(phase.get_name == "main")begin
        `uvm_info(get_name(),"Not yet to end...",UVM_LOW)
        phase.raise_objection(this);
        fork
            begin
                #1;
                this.delay_to_end(phase);
            end
        join_none
    end

-Thank you

23

In reply to ramesh.mr:

source link: