The clock generation running infinitely is not an issue. When the UVM phasing mechanism reaches the end of all phases, a $finish will be called to terminate simulator execution, including the clock.
There must be something else that is preventing the UVM from finishing. If you set UVM_VERBOSITY to UVM_DEBUG, you should see messages as each UVM phase executes.
I think you are blocked in some where in wait statement in some logic or @. One think you can do don not use raise_objection and drop_objection in deep in hierarchical. Just use it in test and enviroment . And put your eot condition in env in run phase. When all sequences is completed test also drop the obection.
i put some display() statments at end of each phase , all messages are displayed.
i put only raise/drop objection in test. the raising is happening but not drop_objection();
the simulation is coming upto line number 5. but not executing line 6.
whenever i will comment line 3(i.e staring master seqr) my simulation is teminating. so i came to know there is problem in master sequencer. how to debug it . please guide me
0.phase.drop_objection(this); i think it is typo or you doing it ??.
Can you make sure that test run phase should have only raise_objection and drop objection.
If its true then only one case it is blocked because of starting master.start() is not completing.
If you raise objection in run phase of each component then it may be the case then some run phases are not completing, so that will block your end of simulation. For example your driver may be the thread which will never end. So your driver may hold the simulation. If you raise objection in env with eot condition done For example ( tx_msg == rx_msg) its mean you are holding simulation to complete your purpose. then drop the objection. In test you are waiting for completion of all sequences.
Hi kbkdec15
I am a beginner in UVM. I also faced the problem of non stopping simulation.
In my case I gave `timescale in my files. Then it worked. I don’t know whether it will work in your case.
In reply to Balu_15:
Hi,
How did you resolve this issue.
I am also facing the same issue, not able to terminate the UVM Simulation.
Please help.
What kind of not stopping do you face? Please explain.
By the way to stop the simulation using UVM there is 1 meachanism. It is the objection mechanism. This is the default way to stop a simulation in the operational mode. And it has to be implemented. If there are no objections the simulation stucks at runtime 0.
If somethinh goes wrong in your simulation and the obejction mechanism does not work you have the option to set a timeout. This becomes active only in the error case.
Thank you for replying.
This issue is resolved, after adding below code to uvm test
task delay_to_end(uvm_phase phase); #1;
`uvm_info(get_name(),$sformatf(“Now to end %s…”,phase.get_name()),UVM_LOW)
phase.drop_objection(this);
endtask
function void phase_ready_to_end(uvm_phase phase);
if(phase.get_name == "main")begin
`uvm_info(get_name(),"Not yet to end...",UVM_LOW)
phase.raise_objection(this);
fork
begin
#1;
this.delay_to_end(phase);
end
join_none
end