How to Terminate UVM simulation?

UVM
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21

In reply to ramesh.mr:

In reply to Balu_15:
Hi,
How did you resolve this issue.
I am also facing the same issue, not able to terminate the UVM Simulation.
Please help.

What kind of not stopping do you face? Please explain.

By the way to stop the simulation using UVM there is 1 meachanism. It is the objection mechanism. This is the default way to stop a simulation in the operational mode. And it has to be implemented. If there are no objections the simulation stucks at runtime 0.
If somethinh goes wrong in your simulation and the obejction mechanism does not work you have the option to set a timeout. This becomes active only in the error case.

22

In reply to chr_sue:

Thank you for replying.
This issue is resolved, after adding below code to uvm test

task delay_to_end(uvm_phase phase);
#1;
`uvm_info(get_name(),$sformatf(“Now to end %s…”,phase.get_name()),UVM_LOW)
phase.drop_objection(this);
endtask

function void phase_ready_to_end(uvm_phase phase);
    if(phase.get_name == "main")begin
        `uvm_info(get_name(),"Not yet to end...",UVM_LOW)
        phase.raise_objection(this);
        fork
            begin
                #1;
                this.delay_to_end(phase);
            end
        join_none
    end

-Thank you

23

In reply to ramesh.mr:

source link:

24

In reply to ramesh.mr:

This is a complex solution to an easy problem.

You should only raise_objection() and drop_objection() in the run_phase() of your tests, using the phase itself (i.e. phase.raise_objection() and phase.drop_objection()).

Your test should look something like this:


task run_phase( uvm_phase phase);
  phase.raise_objection( this );
  test_seq.start( test_sequencer );
  phase.drop_objection( this );
endtask

You should only raise/drop objections one time in the test.