What is the difference between modport and clocking block

SystemVerilog
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1

Hi,

I am not clear about the exact difference between a modport and a clocking block and the purpose of their usage. In some cases, I have observed interface codes implemented with modport/clocking blocks and in some cases I have observed that they have not been used.

Can anyone please highlight the difference between the two and in what cases they are meant to be used?

2

In reply to kautilya1987:

Clocking block is used to introduce input/output sampling/driving delays. Modport defines directions of signals and can be used to represent set of signals.

//By combining clocking block with modport, we define 
//synchronizing point for those signals accessed through
//the modport (e.g. vif.DRV_MP.HREADY)
modport DRV_MP(clocking drv_cb, input reset)
3

In reply to MayurKubavat:
These are two distinct constructs, but there is a slight convenience when used together.

A modport is like a sub-interface to an interface connection. Without modports, interface connections have universal access to all things defined in interface. Modports define a subset of signals for access, as well as their direction. You can think of a modport the same way a module provides a port declaration list as its “boundary” for connections. An SV interface can have multiple “boundaries”, each defined as a separate modport.

A clocking block groups signals and creates a set of corresponding signals that are used for sampling and driving values synchronous to a particular clock. You define the signals to be sampled as ‘inputs’ and the signals to drive as ‘outputs’.

When you put a clocking block in a modport, you get access to all the corresponding clocking block signals as inputs or outputs - there’s no need to list them individually.

4

Thank you Mayur and Dave. Your replies have helped me grasp the concept precisely.

Thanks and Regards

5

Kautilya,

you may want to read this paper to understand the usage further

http://www.verilab.com/files/paper51_taming_tb_timing_FINAL_fixes.pdf

6

In reply to ssureshg_:

When we use both, which signals should we access?

I mean should we access by modport hierarchy or clocking block hierarchy.

7

In reply to krishna4589:

interface.modport.clocking_block is how you access the signals in verif components…

8

In reply to dave_59:

Can you clarify this statement:
“there’s no need to list them individually”

Does that mean that there is no need to use the keywords ‘output’ and ‘input’ as in this example from the 2017 SV specification?

clocking cd1 @(posedge a.clk);
  input data;
  output write;
  inout state;
endclocking

Example Syntax 25-2—Modport clocking declaration syntax from the 2017 spec in 25.5.5 Clocking blocks and modports has a clocking block with the signal directions specified. Seems like potential conflict since the directions are specified on both.

9

In reply to mike_mentor:

No, I mean there’s no need to list the signals and their directions individually in the modport again. You list all the signals in the clocking block and then just put he clocking block in the modport.

10

In reply to dave_59:

I think I understand what you are saying.
Write it like:
modport STB ( clocking sb );
and you get the signals as specified in sb implicitly without listing them.

11

In reply to krishna4589:

Yes I had the same question. Is there any difference between the following ?

  1. interface.modport.clockingblock.signal
  2. interface.clockingblock.signal
12

In reply to gashenoy:

This is unrelated to clocking blocks.

You would only use interface.clockingblock.signal. You never use a modport name in the middle of a hierarchical reference.

interface myItf;
  int A,B,C;
  modport mpX(input A, output B);
  modport mpY(input B, output C);

endinterface
module DUT(myItf.mpX itf);
  // you are only allowed to reference itf.A as an input, and itf.B as an output
endmodule
13

In reply to dave_59:

Hi Dave,
MayurKubavat wrote that clocking blocks are used to insert delays. However, you wrote that this sampling point is defined synchronous with a clock input. Can you introduce arbitrary delays to the sampling interface with the clocking blocks? Is that the correct methodology?
A possible application for this is simulating a netlist with SDF delays and shifting the monitor sample point so that your monitor works beyond the negative edge.
Is there any information about the correct way to do that?
Thanks