What is the difference between modport and clocking block

SystemVerilog
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8

In reply to dave_59:

Can you clarify this statement:
“there’s no need to list them individually”

Does that mean that there is no need to use the keywords ‘output’ and ‘input’ as in this example from the 2017 SV specification?

clocking cd1 @(posedge a.clk);
  input data;
  output write;
  inout state;
endclocking

Example Syntax 25-2—Modport clocking declaration syntax from the 2017 spec in 25.5.5 Clocking blocks and modports has a clocking block with the signal directions specified. Seems like potential conflict since the directions are specified on both.