Verification Academy

Topic	Replies	Views	Activity
Instantiate a uvm class in another class but not to run uvm_phases of class UVM	2	34	May 11, 2024
Dynamic Array declaration SystemVerilog Dynamic-Array	1	32	May 10, 2024
What happens when we assign a value to a net at the time of declaration? SystemVerilog Verilog	4	28	May 10, 2024
About new tech learning UVM SystemVerilog , UVM	0	38	May 10, 2024
Start AHB sequence based on AXI sequence response UVM UVM	0	38	May 10, 2024
Does uvm_config_db pass by value or pass by reference? UVM	1	41	May 9, 2024
Randomize dynamic array with unique values SystemVerilog SystemVerilog , dynamic-arrays , dynamic-array-constraint , systemverilog-constraint , uvm-dynamicarray	8	1355	May 9, 2024
Set_type_override gives compile error UVM set_type_override	3	32	May 8, 2024
Confusion about threads SystemVerilog SystemVerilog	2	42	May 8, 2024
Help me to find the cross coverage percentage? Coverage	4	46	May 8, 2024
Adding Custom Lint Methodology SystemVerilog	1	30	May 8, 2024
QuestaSim Performance Profiler SystemVerilog questasim , performance , simulation-performance	1	24	May 8, 2024
Initializing a Register File SystemVerilog SystemVerilog , initialization , register-file	1	27	May 7, 2024
SVA: Package for dynamic and range delays and repeats SystemVerilog SystemVerilog , dynamic-delays-dynamic-repeats	10	22770	May 7, 2024
System verilog interview questions SystemVerilog SystemVerilog	2	69	May 7, 2024
Generate 200mz clock from 100mhz clock SystemVerilog	4	47	May 7, 2024
Subordinated driver in agent UVM UVM	4	39	May 7, 2024
Discrepancy on legality of the consequent SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA , SVA-Assertion	9	103	May 6, 2024
System verilog interview question SystemVerilog	0	53	May 7, 2024
Logical question SystemVerilog	9	41	May 6, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM UVM , uvm-ral , Ral-write-and-read-methhods	3	2970	May 6, 2024
Randomization of beats SystemVerilog SystemVerilog , UVM	2	42	May 6, 2024
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	19	10741	May 5, 2024
Uvm_sequencer usage UVM UVM	2	52	May 5, 2024
Seq_item_port driver-sequencer - communication issue UVM	2	45	May 5, 2024
Using goto repetition SystemVerilog SystemVerilog , Using-goto-repetition	4	309	May 4, 2024
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation UVM UVM , uvm-driver-monitor-transaction	2	169	May 4, 2024
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object UVM UVM	1	40	May 4, 2024
Overriding UVM_NONE messages UVM UVM-Reporting	4	43	May 4, 2024
Tackling a constraint in post_randomize() SystemVerilog constraint-randomization , systemverilog-constraint	2	59	May 4, 2024