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Reporting Verbosity
Chapter - Mar 31, 2014 by Verification Methodology Team
UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
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Built in Debug
Chapter - Mar 31, 2014 by Verification Methodology Team
Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
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Matlab Integration
Chapter - Mar 31, 2014 by Verification Methodology Team
MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
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UVM Phasing
Chapter - Mar 31, 2014 by Verification Methodology Team
Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.
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Accessing Configuration Resources from a Sequence
Chapter - Mar 31, 2014 by Verification Methodology Team
Sequences often need access to testbench resources such as register models or configuration objects.
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Testbench Configuration
Chapter - Mar 31, 2014 by Verification Methodology Team
One of the key tenets of designing reusable testbenches is to make testbenches as configurable as possible. Doing this means that the testbench and its constituent parts can easily be reused and quickly modified (i.e. reconfigured).
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UVM Packages
Chapter - Mar 31, 2014 by VM Team
A package is a SystemVerilog language construct that enables related declarations and definitions to be grouped together in a package namespace. A package might contain type definitions, constant declarations, functions and class templates. To use a package within a scope, it must be imported, after which its contents can be referenced.
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Dual Top Architecture
Chapter - Mar 31, 2014 by VM Team
The dual top testbench architecture advocated throughout this cookbook enables platform portability - it is fundamental for testbench acceleration using emulation or some other hardware-assisted platform. The HDL top level module encapsulates everything associated directly with the clock cycle-based signal level activity of the RTL DUT, which can be run in simulation or be mapped (i.e. synthesized) onto the emulator.
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Parameterized Tests
Chapter - Mar 31, 2014 by VM Team
SystemVerilog provides a number of ways to pass changeable values through different code structures. Some changeable values must be fixed at elaboration time, others can be changed at run-time after starting a simulation. Changeable values fixed at elaboration time are represented using either a SystemVerilog parameter or `define macro. The use of `define macros causes complications in cases of multiple instances of a module or interface where each instance needs a different changeable value.
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Testbench Build
Chapter - Mar 31, 2014 by VM Team
The first phase of a UVM testbench is the build phase. During this phase, the uvm_component classes that make up the testbench hierarchy are constructed into objects. The construction process works top-down with each level of the hierarchy constructed and configured before the next level down (sometimes also referred to as deferred construction).
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Configuring Sequences
Chapter - Mar 31, 2014 by Verification Methodology Team
A frequently encountered scenario in sequence configuration involves setting up the agent's configuration object, encompassing its constituent components such as the sequencer, driver, monitor, and more.
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UVM Agent
Chapter - Mar 31, 2014 by Verification Methodology Team
A UVM agent is a verification component "kit" for a given logical interface such as APB or USB. The agent includes a SystemVerilog interface encapsulating the corresponding set of interface signals, two SystemVerilog interfaces representing the monitor and driver BFMs, and a SystemVerilog package including the various classes that make up the overall agent class component.
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Emulation
Chapter - Mar 31, 2014 by Verification Methodology Team
Learn all about methodology related to Veloce/TBX Emulation on UVM.
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Using a Parameter Package
Chapter - Mar 31, 2014 by Verification Methodology Team
When a DUT or interface is parameterized, the parameter values are almost always used in the testbench as well.
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Macro Cost-Benefit Analysis
Chapter - Mar 31, 2014 by Verification Methodology Team
Macros can be useful to reduce repetitive typing of small pattern-like code segments, to hide implementation differences or limitations among the simulators from different vendors, or to make critical code segments less error-prone for reuse.
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SystemVerilog Performance Guidelines
Chapter - Mar 31, 2014 by Verification Methodology Team
SystemVerilog shares many common characteristics with mainstream software languages such as C, C++ and Java, and some of the guidelines presented here would be relevant to those languages as well. However, SystemVerilog has some unique capabilities and short-comings which might cause the unwary user to create low performance and memory hungry code without realizing it. These guidelines are aimed at enabling you to identify coding idioms that are likely to affect testbench performance.
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UVM Sequence Items
Chapter - Mar 31, 2014 by VM Team
The UVM stimulus generation process is based on sequences controlling the behavior of drivers by generating sequence_items and sending them to the driver via a sequencer. The framework of the stimulus generation flow is built around the sequence structure for control, but the generation data flow uses sequence_items as the data objects.
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Register Package
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM register model provides a way of tracking the register content of a DUT and a convenience layer for accessing register and memory locations within the DUT.
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UVM Guidelines
Chapter - Mar 31, 2014 by Verification Methodology Team
UVM brings clarity to the SystemVerilog language by providing a structure for how to use the features in SystemVerilog. However, in many cases UVM provides multiple mechanisms to accomplish the same work. This guideline reference is here to provide some structure to UVM in the same way that UVM provides structure to the SystemVerilog language. The UVM library is both a collection of classes and a methodology for how to use those base classes.
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Register Layer Adapter
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM register model access methods generate bus read and write cycles using generic register transactions.
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UVM Performance Guidelines
Chapter - Mar 31, 2014 by Verification Methodology Team
Although the UVM improves verification productivity, there are certain aspects of the methodology that should be used with caution, or perhaps not at all, when it comes to performance and scalability considerations.
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Register-Level Scoreboards
Chapter - Mar 31, 2014 by Verification Methodology Team
The UVM register model shadows the current configuration of a programmable DUT and this makes it a valuable resource for scoreboards that need to be aware of the current DUT state.
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Sequence Driver Connection
Chapter - Mar 31, 2014 by VM Team
The transfer of request and response sequence items between sequences and their target driver is facilitated by a bidirectional TLM communication mechanism implemented in the sequencer. The uvm_driver class contains an uvm_seq_item_pull_port which should be connected to an uvm_seq_item_pull_export in the sequencer associated with the driver. The port and export classes are parameterized with the types of the sequence_items that are going to be used for request and response transactions.
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Don't Forget the Little Things That Can Make Verification Easier
Article - Mar 31, 2014 by Stuart Sutherland - Sutherland-HDL
The little things engineers can do when coding RTL models can add up to a significant boost in verification productivity. A significant portion of SystemVerilog is synthesizable. Taken individually, these synthesizable RTL modeling constructs might seem insignificant, and, therefore, easy to overlook when developing RTL models.
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Taming Power Aware Bugs with Questa®
Article - Mar 31, 2014 by Gaurav Jalan - SmartPlay Technologies
The internet revolution has changed the way we share content, and the mobile revolution has boosted this phenomenon in terms of content creation & consumption.