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1901 Results

  • Evolving Trends in Functional Verification

    2012 Wilson Research Group Functional Verification Study Results

  • What to Expect After Adopting the Metrics

    This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.

  • Metrics in SoC Verification

    In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.

  • Verification Horizons - Volume 8, Issue 2

    "On a recent visit to the Evergreen Aviation & Space Museum in Oregon, I had an opportunity to see some great examples of what, for their time, were incredibly complex pieces of engineering... those successes were the result of early failures where engineers learned the hard way...”

  • Introduction to UVM Connect

    This session introduces UVM Connect and explains the benefits of adoption.

  • Introduction to UVM Connect

  • Connections

  • Connections

    This session shows how to establish connections between components.

  • Converters

    This session shows how to write the converters that are needed to transfer transaction data.

  • Converters

  • UVM Command API

    This session shows how control key aspects of UVM simulation from SystemC.

  • UVM Command API

  • UVM Connect User Guide

  • UVM 1.1b Class Reference

    v1.1b The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.

  • UVM Connect 2.1.4 Kit

  • Verification Horizons - Volume 8, Issue 1

    "Our kitchen renovation is nearly complete... Just as with verification, the key is to have a plan... take as many contingencies into account as you can... and... be able to handle constrained random stimulus.”

  • UVM 1.1a Class Reference

    v1.1a The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.

  • Verification Horizons - Volume 7, Issue 3

    "I find myself thinking of how this (kitchen upgrade) relates to upgrading a verification methodology because I’m sure that, by now, you know that that’s how my mind works.”

  • Testbench Co-Emulation: SystemC & TLM-2.0

    This track advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.

  • Introduction to SystemC & TLM 2.0

    This session provides an introduction of Virtual prototyping and why co-emulation is so attractive for SoC verification.

  • SystemC & TLM-2.0 Testbench Modeling

    This session we will talk about the advantages of using SystemC and OSCI TLM-2.0 standard for testbench modeling.

  • The SCE-MI 2.0 Standard

    This session we will talk about the SCE-MI 2.0 standard in the context of how it can be used with emulation.

  • The OSCI TLM-2.0 Standard

    This session we will talk about the OSCI SystemC TLM-2.0 standard specifically in the context of how it can be used with emulation.

  • Modeling SystemC TLM-2.0 Drivers

    This session we will talk in detail about how to model TLM-2.0 compliant drivers and acceleratable transactors.

  • SystemC & TLM-2.0 Monitors and Talkers

    This session covers the architecture of passive bus monitors and their associated acceleratable transactors.