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2075 Results
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Cocotb Bus Functional Models
Resource (Verification Horizons Blog) - Mar 22, 2021 by Ray Salemi
How to use cocotb to write bus functional models in Python.
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Automatic Formal Verification - Questa Static and Formal Apps
Webinar - Mar 21, 2021 by Walter Gude
In this session, you will gain an understanding of the automatic formal applications that can be used to solve current design and verification challenges.
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Introduction to Coroutines
Resource (Verification Horizons Blog) - Mar 11, 2021 by Ray Salemi
Why a Python feature intended for I/O and asynchronous communication is perfect for verification.
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Celebrating 10 Years of the UVM
Article - Mar 03, 2021 by Mark Peryer
Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.
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Purging CXL Cache Coherency Dilemmas
Article - Mar 03, 2021 by Nikhil Jain, Gaurav Manocha - Siemens EDA
The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.
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What is “Verification” in the Context of DO-254 (Avionics) Programs?
Article - Mar 03, 2021 by Michelle Lange, Jeff Reeve and Tammy Reeve - Patmos Engineering Services
If you are a hardware design or verification engineer, you probably have a good idea of what verification entails. However, add compliance to RTCA/DO-254 as a requirement, and suddenly the definition of “verification” may not be so clear. First, the term “verification” must be understood alongside the synergistic term “validation.” Next, in a DO-254 context, verification spans a wider scope than it does traditionally, so understanding this is crucial.
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Formal Etiquette for Code Coverage Closure
Article - Mar 03, 2021 by Ajeetha Kumari, Arunachalam R and Satheesh Ethiraj - VerifWorks
Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.
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A Formal Verification Technique for Complex Arithmetic Hardware
Article - Mar 03, 2021 by Dr. Sam Elliott - Imagination Technologies
With more emphasis within the electronics industry on high-performance and shorter time to market, the need for high-confidence and high-quality end-to-end verification is becoming more and more important. This is especially true on the heavily optimized arithmetic datapath blocks most used in modern compute and neural network applications. Missed bugs can delay projects and be costly to reputations, and, at the very least, be likely to sap performance.
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Predictable and Scalable End-to-End Formal Verification
Article - Mar 03, 2021 by Dr. Ashish Darbari
In this article, we discuss why formal verification adoption has been limited in industry, and how abstraction-based methodology in formal verification can help DV engineers become successful in adopting formal property checking more widely. Abstraction is the key to obtaining scalability and predictability. It provides an efficient bug-hunting technique and helps in establishing exhaustive proof convergence.
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Enabling RISC-V Based System Development
Article - Mar 03, 2021 by Sandeep Nasam, Sagar Thakran - Logic Fruit Technologies
This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.
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The Six Steps Of RISC-V Processor Verification Including Vector Extensions
Article - Mar 03, 2021 by Larry Lapides
The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.
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Trends in Functional Verification
Webinar - Mar 02, 2021 by Harry Foster
Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.
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I'm Excited About Formal...My Journey From Skeptic To Believer
Webinar - Feb 26, 2021 by Neil Johnson
In this session, you will learn the about unlikely journey into formal for a verification engineer who’s spent an entire career using simulation.
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A Methodology for Comprehensive CDC Analysis
Webinar - Feb 26, 2021 by Atul Sharma
In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
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A Methodology for Comprehensive CDC Analysis
Resource (Slides (.PDF)) - Feb 26, 2021 by Atul Sharma
In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
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The ABC of Formal Verification
Webinar - Feb 11, 2021 by Dr. Ashish Darbari
This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.
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Verification Learns a New Language
Resource (Verification Horizons Blog) - Feb 08, 2021 by Ray Salemi
Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
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I Didn't Know Visualizer Could Do that
Resource (Slides (.PDF)) - Feb 05, 2021 by Rich Edelman
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ISO 26262 Creating an Optimal Safety Architecture
Resource (Slides (.PDF)) - Feb 02, 2021 by Jacob Wiltgen
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ISO 26262 Creating an Optimal Safety Architecture
Session - Feb 02, 2021 by Jacob Wiltgen
In this session you will gain an understanding of the core challenges defining an optimal safety architecture.
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Mil/Aero Analysis Functional Verification Study - 2020
Resource (Paper (.PDF)) - Jan 20, 2021 by Harry Foster
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Mathworks Integration
Resource (Slides (.PDF)) - Dec 29, 2020 by Bob Oden
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Mathworks Integration
Session - Dec 29, 2020 by Bob Oden
In this session you will learn how the UVMF code generator can automatically integrate blocks created using Mathworks® products.
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Embedded Software Debug Using Codelink and Visualizer
Webinar - Dec 08, 2020 by Tomasz Piekarz
In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.
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Visualizer Coverage: Debug and Visualize All Your Coverage
Webinar - Nov 19, 2020 by Athira Panicker
In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.