`define macros usage
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25
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115188
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December 16, 2015
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Checking clock period using system verilog assertion
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30
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53084
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April 5, 2024
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Generate unique elements in an array
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46
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65908
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February 21, 2019
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Fork within loop with join ALL
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35
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55527
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August 10, 2023
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Why do we need virtual interfaces in system verilog?
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24
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65676
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June 4, 2019
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What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example
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32
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54128
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August 8, 2021
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Interview Questions on Assertions
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22
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19555
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September 13, 2024
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Need to Use Variable in Assertions ## Delay
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46
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32547
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July 1, 2021
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Confusion in fork join ... disable fork
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25
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40885
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July 24, 2021
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What difference between @event and wait (event.triggered)?
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14
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53192
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November 25, 2022
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Assert Property vs Cover Property
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19
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45571
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June 11, 2019
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Fork join_none inside for loop
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30
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35239
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June 28, 2022
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P_sequencer and m_sequencer
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11
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54642
|
October 22, 2015
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How to access a DUT signal from a UVM test case class?
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21
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39224
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April 11, 2023
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Queue and mailbox
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13
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47005
|
July 5, 2019
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SVA : using $past
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15
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39968
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October 28, 2020
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Creating new instances of a covergroup using an array
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27
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29598
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July 30, 2017
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Oring of ifdef
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9
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48340
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November 9, 2017
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Constraint randomization of an array
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21
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32490
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June 12, 2024
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Constrain sum of elements in an array
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24
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28869
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October 27, 2024
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Verification of ASYNCHRONOUS FIFO
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21
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29121
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February 18, 2022
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Cannot create a component as it is not registered with a factory
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14
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34159
|
April 30, 2017
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For loop inside fork join_none
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25
|
23928
|
December 20, 2024
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How to Terminate UVM simulation?
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23
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24615
|
April 10, 2020
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P_sequencer / m_sequencer
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9
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36724
|
September 22, 2020
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Range must be bounded by constant expressions
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11
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33375
|
March 2, 2024
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Uvm_config_db usage a big confusion
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10
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33908
|
November 20, 2018
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Why `ifndef and `define are used together?
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13
|
29706
|
July 26, 2019
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Fatal: (SIGSEGV) Bad handle or reference, Error
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22
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22796
|
April 14, 2014
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Automatic variables in fork
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14
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27738
|
February 9, 2022
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Assertion to check stability of a signal for 'n' clocks
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15
|
26653
|
January 29, 2022
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Regarding Method Overriding / Polymorphism SystemVerilog
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25
|
20810
|
August 7, 2018
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Regarding Race Condition
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10
|
17419
|
March 14, 2023
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How to stop or kill the running sequences
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15
|
25346
|
December 3, 2017
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UVM_ERROR
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|
71
|
11664
|
December 15, 2017
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Why system verilog does not allow always block in program scope?
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13
|
23325
|
August 23, 2024
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How to get array of coverpoints
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14
|
22420
|
February 19, 2021
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How to safely delete entries from a queue
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|
12
|
23836
|
May 26, 2017
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Initializing a multidimensional associative array
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11
|
24699
|
October 21, 2020
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Calling task inside function
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|
12
|
22931
|
January 20, 2020
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Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?
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|
9
|
25135
|
April 13, 2015
|
How to exit from simulation on getting UVM_ERROR
|
|
12
|
21859
|
June 3, 2021
|
Casting into an enum
|
|
10
|
23649
|
June 19, 2017
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How to get virtual interface in sequence
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28
|
14105
|
February 18, 2017
|
What is the difference between modport and clocking block
|
|
12
|
21010
|
June 17, 2021
|
SVA: throughout vs until
|
|
9
|
22601
|
March 14, 2020
|
Randomizing a dynamic array size
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|
13
|
18693
|
December 2, 2018
|
Conditional Statement in Assertion Property
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|
11
|
20090
|
May 18, 2018
|
SV assertion for clock gating & Reset check
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|
22
|
13875
|
August 10, 2021
|
Generating random values in increasing order
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|
16
|
15774
|
June 27, 2022
|