Verification Academy

Topic	Replies	Views	Activity
`define macros usage SystemVerilog SystemVerilog	25	115606	December 16, 2015
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	54242	April 5, 2024
Generate unique elements in an array UVM UVM	46	66269	February 21, 2019
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	26	21250	June 18, 2025
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	19	43484	April 28, 2025
Fork within loop with join ALL SystemVerilog SystemVerilog	35	56083	August 10, 2023
Why do we need virtual interfaces in system verilog? SystemVerilog SystemVerilog	24	66532	June 4, 2019
What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example SystemVerilog SystemVerilog	32	55091	August 8, 2021
Verification of ASYNCHRONOUS FIFO UVM SystemVerilog , UVM , assertion , SVA	21	30051	February 18, 2022
Need to Use Variable in Assertions ## Delay SystemVerilog SystemVerilog	46	32844	July 1, 2021
Confusion in fork join ... disable fork SystemVerilog SystemVerilog	25	41188	July 24, 2021
P_sequencer and m_sequencer UVM UVM	13	56122	April 28, 2026
What difference between @event and wait (event.triggered)? UVM UVM , event	14	53866	November 25, 2022
Assert Property vs Cover Property SystemVerilog SystemVerilog	19	46602	June 11, 2019
Fork join_none inside for loop SystemVerilog SystemVerilog	32	36197	March 8, 2025
How to access a DUT signal from a UVM test case class? UVM UVM , hierarchical , reference , DUT	21	39673	April 11, 2023
Queue and mailbox SystemVerilog SystemVerilog	14	47741	July 30, 2025
SVA : using $past SystemVerilog SystemVerilog , SVApast	15	40856	October 28, 2020
Creating new instances of a covergroup using an array Coverage Coverage , Covergroup-instance-for-an-array	27	30185	July 30, 2017
Oring of ifdef SystemVerilog SystemVerilog	9	49274	November 9, 2017
Initializing a multidimensional associative array SystemVerilog SystemVerilog	11	25019	October 21, 2020
Constraint randomization of an array SystemVerilog SystemVerilog	21	32779	June 12, 2024
Constrain sum of elements in an array SystemVerilog SystemVerilog , constraint-randomization , Dynamic-Array	24	29672	October 27, 2024
Cannot create a component as it is not registered with a factory UVM UVM	14	34667	April 30, 2017
P_sequencer / m_sequencer UVM UVM	11	37039	February 13, 2026
For loop inside fork join_none SystemVerilog SystemVerilog	25	24846	December 20, 2024
How to Terminate UVM simulation? UVM UVM , simulation-Terminate	23	24966	April 10, 2020
Range must be bounded by constant expressions SystemVerilog SystemVerilog	11	33996	March 2, 2024
Uvm_config_db usage a big confusion UVM UVM , uvm_config_db	10	34582	November 20, 2018
Why `ifndef and `define are used together? OVM OVM	13	30162	July 26, 2019
Fatal: (SIGSEGV) Bad handle or reference, Error UVM UVM	22	23348	April 14, 2014
Automatic variables in fork SystemVerilog SystemVerilog	14	28495	February 9, 2022
Regarding Method Overriding / Polymorphism SystemVerilog SystemVerilog SystemVerilog , Polymorphism , Method-Overriding	26	21109	August 15, 2025
Assertion to check stability of a signal for 'n' clocks SystemVerilog SystemVerilog , stability-of-a-signal	15	27147	January 29, 2022
Regarding Race Condition SystemVerilog SystemVerilog	10	17845	March 14, 2023
How to stop or kill the running sequences UVM UVM , end-of-test-mechanism-in-UVM , sequence-and-sequencer , testcase	15	26013	December 3, 2017
UVM_ERROR UVM UVM	71	11825	December 15, 2017
Why system verilog does not allow always block in program scope? SystemVerilog SystemVerilog	13	23607	August 23, 2024
How to get array of coverpoints Coverage Coverage	14	22785	February 19, 2021
How to safely delete entries from a queue SystemVerilog SystemVerilog	12	24442	May 26, 2017
Calling task inside function SystemVerilog SystemVerilog	12	23588	January 20, 2020
Casting into an enum SystemVerilog SystemVerilog	10	24410	June 19, 2017
Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion? UVM UVM	9	25304	April 13, 2015
How to exit from simulation on getting UVM_ERROR UVM UVM	12	22117	June 3, 2021
How to get virtual interface in sequence UVM UVM	28	14494	February 18, 2017
What is the difference between modport and clocking block SystemVerilog SystemVerilog , modport-clocking-block	12	21612	June 17, 2021
SVA: throughout vs until SystemVerilog SystemVerilog , SVA , througout	9	23566	March 14, 2020
Randomizing a dynamic array size SystemVerilog SystemVerilog , rand_mode-dynamic-array , system-verilog-constraints , Question	13	18971	December 2, 2018
SV assertion for clock gating & Reset check SystemVerilog SystemVerilog	22	14320	August 10, 2021
How do I define an associative array of queues? SystemVerilog SystemVerilog , associative-array , Queues-in-system-verilog , systemverilog-Arrays	15	16565	August 19, 2022