Verification Academy

Topic	Replies	Views	Activity
`define macros usage SystemVerilog SystemVerilog	25	115392	December 16, 2015
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	53662	April 5, 2024
Generate unique elements in an array UVM UVM	46	66071	February 21, 2019
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	19	42999	April 28, 2025
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	26	20444	June 18, 2025
Fork within loop with join ALL SystemVerilog SystemVerilog	35	55799	August 10, 2023
Why do we need virtual interfaces in system verilog? SystemVerilog SystemVerilog	24	66102	June 4, 2019
What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example SystemVerilog SystemVerilog	32	54609	August 8, 2021
Verification of ASYNCHRONOUS FIFO UVM SystemVerilog , UVM , assertion , SVA	21	29554	February 18, 2022
Need to Use Variable in Assertions ## Delay SystemVerilog SystemVerilog	46	32674	July 1, 2021
Confusion in fork join ... disable fork SystemVerilog SystemVerilog	25	41016	July 24, 2021
What difference between @event and wait (event.triggered)? UVM UVM , event	14	53562	November 25, 2022
Assert Property vs Cover Property SystemVerilog SystemVerilog	19	46066	June 11, 2019
Fork join_none inside for loop SystemVerilog SystemVerilog	32	35786	March 8, 2025
P_sequencer and m_sequencer UVM UVM	11	55357	October 22, 2015
How to access a DUT signal from a UVM test case class? UVM UVM , hierarchical , reference , DUT	21	39472	April 11, 2023
Queue and mailbox SystemVerilog SystemVerilog	14	47399	July 30, 2025
SVA : using $past SystemVerilog SystemVerilog , SVApast	15	40402	October 28, 2020
Creating new instances of a covergroup using an array Coverage Coverage , Covergroup-instance-for-an-array	27	29889	July 30, 2017
Oring of ifdef SystemVerilog SystemVerilog	9	48781	November 9, 2017
Constraint randomization of an array SystemVerilog SystemVerilog	21	32646	June 12, 2024
Constrain sum of elements in an array SystemVerilog SystemVerilog , constraint-randomization , Dynamic-Array	24	29316	October 27, 2024
Cannot create a component as it is not registered with a factory UVM UVM	14	34434	April 30, 2017
For loop inside fork join_none SystemVerilog SystemVerilog	25	24387	December 20, 2024
How to Terminate UVM simulation? UVM UVM , simulation-Terminate	23	24822	April 10, 2020
Range must be bounded by constant expressions SystemVerilog SystemVerilog	11	33695	March 2, 2024
P_sequencer / m_sequencer UVM UVM	9	36819	September 22, 2020
Uvm_config_db usage a big confusion UVM UVM , uvm_config_db	10	34264	November 20, 2018
Why `ifndef and `define are used together? OVM OVM	13	29952	July 26, 2019
Fatal: (SIGSEGV) Bad handle or reference, Error UVM UVM	22	23075	April 14, 2014
Regarding Method Overriding / Polymorphism SystemVerilog SystemVerilog SystemVerilog , Polymorphism , Method-Overriding	26	20957	August 15, 2025
Automatic variables in fork SystemVerilog SystemVerilog	14	28112	February 9, 2022
Assertion to check stability of a signal for 'n' clocks SystemVerilog SystemVerilog , stability-of-a-signal	15	26923	January 29, 2022
Regarding Race Condition SystemVerilog SystemVerilog	10	17661	March 14, 2023
How to stop or kill the running sequences UVM UVM , end-of-test-mechanism-in-UVM , sequence-and-sequencer , testcase	15	25677	December 3, 2017
UVM_ERROR UVM UVM	71	11720	December 15, 2017
Why system verilog does not allow always block in program scope? SystemVerilog SystemVerilog	13	23462	August 23, 2024
How to get array of coverpoints Coverage Coverage	14	22622	February 19, 2021
How to safely delete entries from a queue SystemVerilog SystemVerilog	12	24171	May 26, 2017
Initializing a multidimensional associative array SystemVerilog SystemVerilog	11	24872	October 21, 2020
Calling task inside function SystemVerilog SystemVerilog	12	23278	January 20, 2020
Casting into an enum SystemVerilog SystemVerilog	10	24043	June 19, 2017
Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion? UVM UVM	9	25197	April 13, 2015
How to exit from simulation on getting UVM_ERROR UVM UVM	12	21988	June 3, 2021
How to get virtual interface in sequence UVM UVM	28	14306	February 18, 2017
What is the difference between modport and clocking block SystemVerilog SystemVerilog , modport-clocking-block	12	21328	June 17, 2021
SVA: throughout vs until SystemVerilog SystemVerilog , SVA , througout	9	23082	March 14, 2020
Randomizing a dynamic array size SystemVerilog SystemVerilog , rand_mode-dynamic-array , system-verilog-constraints , Question	13	18820	December 2, 2018
SV assertion for clock gating & Reset check SystemVerilog SystemVerilog	22	14105	August 10, 2021
Generating random values in increasing order SystemVerilog SystemVerilog , System-Verilog , constrained-random-generation	16	15895	June 27, 2022