Verification Academy

Topic	Replies	Views	Activity
`define macros usage SystemVerilog SystemVerilog	25	115149	December 16, 2015
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	52981	April 5, 2024
Generate unique elements in an array UVM UVM	46	65878	February 21, 2019
Fork within loop with join ALL SystemVerilog SystemVerilog	35	55471	August 10, 2023
Why do we need virtual interfaces in system verilog? SystemVerilog SystemVerilog	24	65614	June 4, 2019
What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example SystemVerilog SystemVerilog	32	54055	August 8, 2021
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	22	19461	September 13, 2024
Need to Use Variable in Assertions ## Delay SystemVerilog SystemVerilog	46	32519	July 1, 2021
Confusion in fork join ... disable fork SystemVerilog SystemVerilog	25	40871	July 24, 2021
What difference between @event and wait (event.triggered)? UVM UVM , event	14	53136	November 25, 2022
Assert Property vs Cover Property SystemVerilog SystemVerilog	19	45495	June 11, 2019
Fork join_none inside for loop SystemVerilog SystemVerilog	30	35163	June 28, 2022
P_sequencer and m_sequencer UVM UVM	11	54527	October 22, 2015
How to access a DUT signal from a UVM test case class? UVM UVM , hierarchical , reference , DUT	21	39177	April 11, 2023
Queue and mailbox SystemVerilog SystemVerilog	13	46950	July 5, 2019
SVA : using $past SystemVerilog SystemVerilog , SVApast	15	39905	October 28, 2020
Creating new instances of a covergroup using an array Coverage Coverage , Covergroup-instance-for-an-array	27	29555	July 30, 2017
Oring of ifdef SystemVerilog SystemVerilog	9	48268	November 9, 2017
Constraint randomization of an array SystemVerilog SystemVerilog	21	32469	June 12, 2024
Constrain sum of elements in an array SystemVerilog SystemVerilog , constraint-randomization , Dynamic-Array	24	28790	October 27, 2024
Verification of ASYNCHRONOUS FIFO UVM SystemVerilog , UVM , assertion , SVA	21	29051	February 18, 2022
Cannot create a component as it is not registered with a factory UVM UVM	14	34110	April 30, 2017
For loop inside fork join_none SystemVerilog SystemVerilog	25	23837	December 20, 2024
How to Terminate UVM simulation? UVM UVM , simulation-Terminate	23	24583	April 10, 2020
P_sequencer / m_sequencer UVM UVM	9	36707	September 22, 2020
Range must be bounded by constant expressions SystemVerilog SystemVerilog	11	33320	March 2, 2024
Uvm_config_db usage a big confusion UVM UVM , uvm_config_db	10	33849	November 20, 2018
Why `ifndef and `define are used together? OVM OVM	13	29662	July 26, 2019
Fatal: (SIGSEGV) Bad handle or reference, Error UVM UVM	22	22746	April 14, 2014
Automatic variables in fork SystemVerilog SystemVerilog	14	27675	February 9, 2022
Assertion to check stability of a signal for 'n' clocks SystemVerilog SystemVerilog , stability-of-a-signal	15	26600	January 29, 2022
Regarding Method Overriding / Polymorphism SystemVerilog SystemVerilog SystemVerilog , Polymorphism , Method-Overriding	25	20783	August 7, 2018
Regarding Race Condition SystemVerilog SystemVerilog	10	17374	March 14, 2023
How to stop or kill the running sequences UVM UVM , end-of-test-mechanism-in-UVM , sequence-and-sequencer , testcase	15	25297	December 3, 2017
UVM_ERROR UVM UVM	71	11647	December 15, 2017
Why system verilog does not allow always block in program scope? SystemVerilog SystemVerilog	13	23298	August 23, 2024
How to get array of coverpoints Coverage Coverage	14	22379	February 19, 2021
How to safely delete entries from a queue SystemVerilog SystemVerilog	12	23781	May 26, 2017
Initializing a multidimensional associative array SystemVerilog SystemVerilog	11	24669	October 21, 2020
Calling task inside function SystemVerilog SystemVerilog	12	22874	January 20, 2020
Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion? UVM UVM	9	25125	April 13, 2015
How to exit from simulation on getting UVM_ERROR UVM UVM	12	21831	June 3, 2021
Casting into an enum SystemVerilog SystemVerilog	10	23587	June 19, 2017
How to get virtual interface in sequence UVM UVM	28	14062	February 18, 2017
What is the difference between modport and clocking block SystemVerilog SystemVerilog , modport-clocking-block	12	20960	June 17, 2021
SVA: throughout vs until SystemVerilog SystemVerilog , SVA , througout	9	22526	March 14, 2020
Randomizing a dynamic array size SystemVerilog SystemVerilog , rand_mode-dynamic-array , system-verilog-constraints , Question	13	18671	December 2, 2018
Conditional Statement in Assertion Property SystemVerilog SystemVerilog , assertion , conditional-statement	11	20032	May 18, 2018
SV assertion for clock gating & Reset check SystemVerilog SystemVerilog	22	13839	August 10, 2021
Generating random values in increasing order SystemVerilog SystemVerilog , System-Verilog , constrained-random-generation	16	15755	June 27, 2022