Verification Academy

Topic	Replies	Views	Activity
`define macros usage SystemVerilog SystemVerilog	25	114553	December 16, 2015
Generate unique elements in an array UVM UVM	46	65320	February 21, 2019
Fork within loop with join ALL SystemVerilog SystemVerilog	35	54848	August 10, 2023
Why do we need virtual interfaces in system verilog? SystemVerilog SystemVerilog	24	64966	June 4, 2019
What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example SystemVerilog SystemVerilog	32	53315	August 8, 2021
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	52023	April 5, 2024
Need to Use Variable in Assertions ## Delay SystemVerilog SystemVerilog	46	32086	July 1, 2021
Confusion in fork join ... disable fork SystemVerilog SystemVerilog	25	40473	July 24, 2021
What difference between @event and wait (event.triggered)? UVM UVM , event	14	52483	November 25, 2022
Assert Property vs Cover Property SystemVerilog SystemVerilog	19	44745	June 11, 2019
Fork join_none inside for loop SystemVerilog SystemVerilog	30	34417	June 28, 2022
P_sequencer and m_sequencer UVM UVM	11	53573	October 22, 2015
How to access a DUT signal from a UVM test case class? UVM UVM , hierarchical , reference , DUT	21	38537	April 11, 2023
Queue and mailbox SystemVerilog SystemVerilog	13	46294	July 5, 2019
SVA : using $past SystemVerilog SystemVerilog , SVApast	15	39221	October 28, 2020
Creating new instances of a covergroup using an array Coverage Coverage , Covergroup-instance-for-an-array	27	28966	July 30, 2017
Oring of ifdef SystemVerilog SystemVerilog	9	47551	November 9, 2017
Constraint randomization of an array SystemVerilog SystemVerilog	20	31996	January 31, 2019
Verification of ASYNCHRONOUS FIFO UVM SystemVerilog , UVM , assertion , SVA	21	28314	February 18, 2022
Constrain sum of elements in an array SystemVerilog SystemVerilog , constraint-randomization , Dynamic-Array	20	27969	May 22, 2023
How to Terminate UVM simulation? UVM UVM , simulation-Terminate	23	24031	April 10, 2020
P_sequencer / m_sequencer UVM UVM	9	36355	September 22, 2020
Range must be bounded by constant expressions SystemVerilog SystemVerilog	11	32688	March 2, 2024
Uvm_config_db usage a big confusion UVM UVM , uvm_config_db	10	33213	November 20, 2018
Why `ifndef and `define are used together? OVM OVM	13	29097	July 26, 2019
Fatal: (SIGSEGV) Bad handle or reference, Error UVM UVM	22	22127	April 14, 2014
Automatic variables in fork SystemVerilog SystemVerilog	14	27027	February 9, 2022
Assertion to check stability of a signal for 'n' clocks SystemVerilog SystemVerilog , stability-of-a-signal	15	26032	January 29, 2022
Regarding Method Overriding / Polymorphism SystemVerilog SystemVerilog SystemVerilog , Polymorphism , Method-Overriding	25	20379	August 7, 2018
How to stop or kill the running sequences UVM UVM , end-of-test-mechanism-in-UVM , sequence-and-sequencer , testcase	15	24641	December 3, 2017
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	24	19335	February 29, 2024
UVM_ERROR UVM UVM	71	11278	December 15, 2017
How to get array of coverpoints Coverage Coverage	14	21889	February 19, 2021
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	20	18490	February 22, 2024
Initializing a multidimensional associative array SystemVerilog SystemVerilog	11	24208	October 21, 2020
How to safely delete entries from a queue SystemVerilog SystemVerilog	12	23160	May 26, 2017
Calling task inside function SystemVerilog SystemVerilog	12	22235	January 20, 2020
Why system verilog does not allow always block in program scope? SystemVerilog SystemVerilog	11	22800	May 19, 2016
Why is the build() phase in UVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion? UVM UVM	9	24826	April 13, 2015
How to exit from simulation on getting UVM_ERROR UVM UVM	12	21405	June 3, 2021
Casting into an enum SystemVerilog SystemVerilog	10	22922	June 19, 2017
What is the difference between modport and clocking block SystemVerilog SystemVerilog , modport-clocking-block	12	20309	June 17, 2021
How to get virtual interface in sequence UVM UVM	28	13534	February 18, 2017
SVA: throughout vs until SystemVerilog SystemVerilog , SVA , througout	9	21788	March 14, 2020
Randomizing a dynamic array size SystemVerilog SystemVerilog , rand_mode-dynamic-array , system-verilog-constraints , Question	13	18250	December 2, 2018
Conditional Statement in Assertion Property SystemVerilog SystemVerilog , assertion , conditional-statement	11	19396	May 18, 2018
SV assertion for clock gating & Reset check SystemVerilog SystemVerilog	22	13246	August 10, 2021
Generating random values in increasing order SystemVerilog SystemVerilog , System-Verilog , constrained-random-generation	16	15326	June 27, 2022
A constraint to generate odd_even_odd....... etc sequence SystemVerilog SystemVerilog , constraint , randomization	9	19844	June 9, 2017
Coverpoint for an array or queue Coverage Coverage	9	19362	May 31, 2021