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Selective hardening in space applications
Resource (Verification Horizons Blog) - Oct 24, 2023 by Jacob Wiltgen
The space sector continues to experience disruption as innovation drives the creation of new business models across government and commercial entities. Low Earth Orbit (LEO) constellations, Traffic and Management applications, and advanced communication systems are just a few examples where innovation is driving the next generation of semiconductor development targeted for space based applications.
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Similar but Different – The Tale of Transient and Permanent Faults
Resource (Paper (.PDF)) - Oct 18, 2023 by Charles Battikha
This paper highlights the fundamental differences between permanent and transient faults on digital circuits, and why this distinction is important in the context of the ISO 26262:2018 functional safety standard.
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Similar but Different – The Tale of Transient and Permanent Faults
Paper - Oct 18, 2023 by Charles Battikha
When determining whether an IC is safe from random hardware faults, applying safety metrics such as PMHF, SPFM, and LFM, engineers must analyze both transient and permanent faults. This paper highlights the fundamental differences between permanent and transient faults on digital circuits, and why this distinction is important in the context of the ISO 26262:2018 functional safety standard.
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Starting Your UVM Simulation
Resource (Verification Horizons Blog) - Oct 10, 2023 by Chris Spear
What happens when you start your simulation with a UVM testbench? Where should you put the uvm_config_db::set() calls to send the virtual interface to the test class? Are there potential race conditions? And what happens when your test is over?
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Selective Radiation Mitigation for Integrated Circuits
Paper - Oct 09, 2023 by Jacob Wiltgen
Shortened lifecycles and cost reduction coupled with the demand for advanced capabilities continue to challenge project teams delivering IC into space systems. To meet these demands, project teams continue evolving across all aspects of the lifecycle, including the implementation and verification of mitigation protections against single event effects. This paper defines a methodology that enables teams to perform selective radiation mitigation and implement an optimal mitigation architecture.
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Selective Radiation Mitigation for Integrated Circuits
Resource (Paper (.PDF)) - Oct 09, 2023 by Jacob Wiltgen
This paper defines a methodology that enables teams to perform selective radiation mitigation and implement an optimal mitigation architecture.
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Austemper Analysis and Fault Simulation
Resource (Fact Sheet) - Oct 02, 2023 by Ann Keffer
The Austemper closed-loop safety flow analyzes and validates the resilience of mission-critical designs to mitigate random faults. Early, accurate safety analysis with automatic identification of where to add safety enhancements, combined with fast fault simulation provides an efficient closed-loop safety flow for the development of automotive ICs.
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Questa Formal Apps Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Even the most carefully designed testbench is inherently incomplete since constrained-random methods cannot hit every corner case. Unfortunately, even after 100% functional coverage is achieved there can still be showstopper bugs hiding in unimagined state spaces. Questa Formal Apps statically analyze a design’s behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner.
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Questa Verification IQ Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Big data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. Verification needs to transform in step, so we can predict which test to run next, the root cause of a failure, and what stimulus is required. Questa Verification IQ is the Siemens EDA collaborative, data-driven verification solution that transforms the verification process using analytics, collaboration, and traceability.
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Questa RDC Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa RDC identifies reset domains, the related clock domains, and reset domain synchronizers, as well as low power structures via the Unified Power Format (UPF). The technology then exhaustively checks for any potential RDC errors, statically verifying that all signals crossing asynchronous reset and clock domain boundaries are guarded by RDC synchronizers. Any discovered issues are illustrated using familiar schematic and waveform displays.
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Questa Lint Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Lint provides actionable results with low noise. Questa Lint reviews reported issues, then uses its deep understanding of every issue known to provide results different than inferred intent (as well as those known to cause false violations), to adapt the results. This results in Questa Lint reporting only the issues that need to be fixed, and in the order of those that matter most, resulting in actionable results and faster fix cycles.
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Austemper Analysis and Fault Simulation
Resource (Fact Sheet) - Oct 01, 2023 by
The Austemper closed-loop safety flow analyzes and validates the resilience of mission-critical designs to mitigate random faults. Early, accurate safety analysis with automatic identification of where to add safety enhancements, combined with fast fault simulation provides an efficient closed-loop safety flow for the development of automotive ICs.
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QuestaSim Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
The QuestaSim™ verification solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. In addition to the sheer size of designs and the inclusion of multiple embedded processors and advanced interconnect systems, the increase in software content and the configurability required by multi-platform design requires a functional verification solution that unifies a broad arsenal of verification features.
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Questa Verification IQ Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Verification IQ is implemented in a web-based application framework providing scalable verification management with zero install for device and OS independence. It supports public, private, and hybrid cloud configurations with native collaboration and centralized data access. Questa Verification IQ presents all tasks within a familiar, modern, user interface protected by a secure, login-based licensing model, and it supports URL sharing and user-based notification systems.
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Questa Signoff CDC Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Signoff CDC uses automated, advanced structural analysis algorithms optimized for gate-level analysis, as well as automated leveraging of waiver and CDC path information from Questa CDC RTL analysis for exacting, “low noise” results.
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Questa Visualizer Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago; for example, clocking requirements, security requirements, safety requirements, and requirements.
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Exploring the Multifaceted Landscape of Formal Coverage
Webinar - Sep 20, 2023 by Nicolae Tusinschi
In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.
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UVM Framework Release 2023.3
Resource (Tarball) - Sep 08, 2023 by Bob Oden
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Digital Transformation: How Siemens EDA Helps You Engineer a Smarter Future Faster
Resource (Paper (.PDF)) - Sep 02, 2023 by Mike Santarini - Siemens EDA
This pace of digital transformation will accelerate even more rapidly as more companies begin to incorporate artificial intelligence (AI) and machine learning (ML) into their systems to leverage and even monetize the exponentially increasing amount of data produced by seemingly “everything digital.” Siemens EDA is dedicated to helping more companies advance in their digital transformation and engineer a smarter future faster.
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Breaking the RISC-V Processor Customization Barrier with Formal Verification
Webinar - Jul 19, 2023 by Sven Beyer
In this session, you will learn the role that formal has in state-of-the-art processor DV and the QoS processor core verification workflow.
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Revolutionizing Circuit Design: Unveiling the latest updates and roadmap of Questa Simulation Tools
Resource (Slides (.PDF)) - Jun 22, 2023 by Moses Satyasekaran
Discover how our cutting-edge Questa Simulation tools revolutionize the industry and deliver users' best product experience. During this session, we will unveil our latest product updates and discuss our exciting investments in the future of our product roadmap. Plus, you'll get a behind-the-scenes look at our strategic investments in the product, including our plans for expanding functionality, enhancing performance, and delivering even greater value to our users.
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Third-Party IP Assurance Using AutoCheck
Resource (Slides (.PDF)) - Jun 22, 2023 by Luke Wolff - VeriSi Corporation
The use of Third-Party Intellectual Property (3PIP) in Aerospace and Defense (A&D) designs raises concerns about the level of trust that can be placed in 3PIP. In the absence of a full testbench with documentation what can be done to improve trust in 3PIP? Questa Formal AutoCheck provides an option for assessing designs with a low threshold for design comprehension. This presentation will explore the application of AutoFormal to 3PIP and provide examples of issues found in real 3PIP.
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Simple, Maintainable, Accessible, and Reusable Testplans
Resource (Slides (.PDF)) - Jun 22, 2023 by Toanl Nquyer - VeriSi Corporation
Testplans are a necessary step in the verification process but can be cumbersome depending on the user’s development environment. Available software may not be compatible with testplan plug-ins, and frustrating idiosyncrasies can arise during XML export. The YAML format is very similar to XML but is much more accessible and maintainable. This presentation discusses the benefits of using the YAML format as a base for testplan generation.
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Questa Verification IQ: Boost verification predictability and efficiency
Resource (Slides (.PDF)) - Jun 22, 2023 by Jonathan Stanley
Big Data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. In this session, you will learn how Siemens’s latest offering, Questa Verification IQ (VIQ), can help you accelerate coverage closure, better manage your test and compute resources, and provide overall faster verification turnaround times by using analytics, collaboration, and traceability.
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Debugging RTL and UVM in Post-sim and Live-sim in the Visualizer Debug Environment
Resource (Slides (.PDF)) - Jun 22, 2023 by Rich Edelman
The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer and the Questa QIS technology ensures the fastest simulation while logging and prevents mismatches between regression simulations and debug simulations. Visualizer raises the debug abstraction using the Transaction viewer, the FSM view, the logic cone and the schematic viewer. Complex UVM testbench can be debugged easily in the wave window.