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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
      • Introduction to DO-254
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      • Power Aware CDC Verification
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      • SystemVerilog OOP for UVM Verification

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      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
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      • Verification Planning and Management
      • VHDL-2008 Why It Matters

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      • Formal-Based Technology: Automatic Formal Solutions
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      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
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      • Bus Protocol Coverage
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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      • Low Power Verification - 4/29
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Debug
  • Visualizer™ Debug Environment
  • Adding Signals to the Wave Window

Adding Signals to the Wave Window

  • Introduction
  • Video
  • Related Resources
Other sessions in this series:
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Visualizer Debug Environment - Adding Signals to the Wave Window

Session Details

One of the primary ways to debug in Visualizer is through adding signals in Wave Window. Visualizer had enabled users to add signals to wave window through multiple entry points. In this session we will discuss the many ways you can add signals to the wave window in Visualizer.

Tom Kiley
Debug
Walk
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