Verification Academy

Topic	Replies	Views	Activity
Bit slicing in systemVerilog SystemVerilog SystemVerilog	12	80857	January 4, 2019
What is the difference between @(posedge clk) begin end.... and @(posedge clk);? SystemVerilog SystemVerilog , Race-condition , posedge , posedge-clk , posedge-clk-begin	15	68495	November 16, 2018
How to force dut internal signals in UVM environment UVM UVM	11	65271	September 30, 2020
Bitwise toggle coverage for a bitvector SystemVerilog SystemVerilog	31	39303	May 10, 2020
Confusion over casting of classes SystemVerilog SystemVerilog	14	56161	October 25, 2018
Importance of the clone( ) method OVM OVM	17	45145	September 25, 2021
About type_id::create() OVM OVM	14	48107	January 24, 2020
SystemVerilog $feof() SystemVerilog SystemVerilog	18	42000	October 29, 2019
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	17	42146	July 23, 2024
Difference Between UVM_OBJECT and UVM_COMPONENT UVM UVM , UVM_OBJECT-and-UVM_COMPONENT	13	47154	January 15, 2018
Usage of Var SystemVerilog SystemVerilog , reg-wire-logic	11	26678	March 15, 2023
Calling randomize() from a sequence OVM OVM	19	34230	July 1, 2009
How to define cross coverage for the selected range SystemVerilog SystemVerilog	12	39700	March 10, 2017
Cannot create a component as it is not registered with a factory UVM UVM	14	33999	April 30, 2017
How do I connect inout ports? SystemVerilog SystemVerilog , Inout-port	10	39441	May 16, 2021
Generate block in SV SystemVerilog SystemVerilog	9	37915	December 19, 2016
OVM wrapper for Verilog Bfms? OVM OVM	26	22876	February 27, 2019
How to define a condition for a covergroup (using iff)? SystemVerilog SystemVerilog	17	27864	November 7, 2021
Do you `include or import? OVM OVM	11	34106	July 13, 2010
How to manage the seed of randomization? OVM OVM	9	34388	March 15, 2019
Uvm_component_utils with parameters UVM UVM	13	27721	January 24, 2020
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	26	19928	November 14, 2024
For loop inside fork join_none SystemVerilog SystemVerilog	18	23670	January 28, 2023
USING std::randomize functio SystemVerilog SystemVerilog	12	28231	October 31, 2014
Virtual interface resolution cannot find a matching instance of interface OVM OVM	21	21685	November 21, 2016
How does forever behaves in fork block SystemVerilog SystemVerilog	13	26516	October 2, 2020
Randomizing the prime numbers SystemVerilog SystemVerilog , array-randomization , constraint-foreach-loop , prime-number-constraint	10	16734	June 26, 2024
Always block in task SystemVerilog SystemVerilog	17	23035	February 27, 2024
Accessing a generate block hierarchy SystemVerilog SystemVerilog	12	26459	August 31, 2016
Vim Syntax highlighting for SystemVerilog and OVM OVM OVM	11	27165	March 4, 2011
How can I assign one interface to another interface without manually connecting all signals? SystemVerilog SystemVerilog , Interfaces	11	14958	August 30, 2022
Function new() overriding ? why should we call super.new() function in derived class constructor? SystemVerilog SystemVerilog	13	24417	July 13, 2018
Distributed weightage constraint SystemVerilog SystemVerilog	9	28753	January 19, 2021
The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it UVM UVM , UVM-SystemVerilog	38	14387	November 30, 2021
Hierarchial access for DUT signals OVM OVM	15	22012	November 29, 2016
Out of order in driver and scoreboard UVM UVM , uvm_driver , uvm_scoreboard	11	25143	October 15, 2019
UVM Test is not comming out UVM UVM	17	19590	July 9, 2016
Please format your code with markdown or <code> </code> tags Announcements Announcements	9	25153	August 8, 2024
" uvm_do_on_with " constraint issue UVM UVM	9	24996	August 8, 2020
OVM Verbosity OVM OVM	13	20828	August 27, 2009
SVA: Package for dynamic and range delays and repeats SystemVerilog SystemVerilog , dynamic-delays-dynamic-repeats	10	23361	May 7, 2024
Array sum() method issue SystemVerilog SystemVerilog	11	21658	July 14, 2021
UVM Register Kit for OVM 2.1.2 Downloads UVM , Downloads , registers	20	16210	May 4, 2012
Global_stop_request() & $finish OVM OVM	17	17423	June 19, 2009
Using 'ref' with variables in interface SystemVerilog SystemVerilog	14	18624	April 11, 2019
How to use tlm_analysis_fifo? UVM UVM	14	18510	July 17, 2024
Method/function overloading SystemVerilog SystemVerilog	15	17775	November 7, 2024
Array of cover points in a covergroup Coverage Coverage , functional-coverage	12	19616	July 14, 2021
Set_type_override_by_type OVM OVM	9	22310	April 7, 2017
Assigning elements of an virtual interface array? OVM OVM	14	18055	May 8, 2008