Bit slicing in systemVerilog

SystemVerilog
1

Hi,

I’m looking for a technique to do bit slicing in systemVerilog.

for(int i=0; i<10; i++)
data[(i8)+7 : (i8)] = temp[(i8)+7 : (i8)];

if i use the above syntax irun tool is giving compilation error.
“Illegal operand for constant expression [4(IEEE)]”

Please help me out.

Thanks,
Noorulla
(noorulla.mohammad@gmail.com)

2

Use this Verlog-2001 trick:

for(int i=0; i<10; i++)
  data[(i*8)+7 -: 8] = temp[(i*8)+7 -: 8];

HTH
Ajeetha, CVC

3

In reply to Ajeetha Kumari CVC:

The problem is in my vector both the Min and Max are variable length.
like,
data[(i8)+7 : (i8)] as i varies the ranges varies from 7:0, 15:8 etc. does the above statement behaves the similar way.

Thanks,
Noorulla

4

Noorulla,

Try this:

data[i*7 +:8] = temp[i*7 +:8];

The above is Verilog 2005 syntax; 8 is the width of the slice and will be added to i*7 every iteration through the loop.

5

Noorulla,

Perhaps you should explain why you need bit-slicing, and how data and temp are declared. If they are

bit [100:0] data,temp;

then the following should work

data [79:0] = temp[79:0];

Maybe you did not post your example correctly.

6

In reply to MdNoorulla:

Noorulla,
Suggest you read V2K LRM on this. As you mentioned:

data[(i8)+7 : (i8)] as i varies the ranges varies from 7:0, 15:8

In this case, your slice-width is indeed a CONSTANT and not variable. Only the position is run-time variable. So the following should work:

data[(i*8)+7 -: 8]

Try and let us know if it doesn’t. Post a full code if you still see issue.

HTH
Ajeetha, CVC

7

In reply to dave_59:

Hi Dave,

I just copied a part of my code and simiplified. My requirement is i have a 256 bit width data bus. I need to read and write to the sparse memory (assosiative array of bytes) based on some conditions like,
number of bytes to read from memory, mask bits etc. i took the data bus as bit [255:0] DATA.

Thanks,
Noorulla

8

https://leventozturk.com/engineering/slicer takes an input stream or file as binary data and slices into chunks of desired number of bits online.

9

Hi Ajeetha,

Tried the below code for variable length part select.

reg [143:0] file_data_re0;
  reg [143:0] file_data_im0;
  
  bit [11:0] data_re0;
  bit [11:0] data_im0;
  
for(i=0; i<=11;i++) begin
       file_data_re0[((i+1)*12)-1 +: i*12] = data_re0;
       file_data_im0[((i+1)*12)-1 +: i*12] = data_im0;
 end

getting the following error
Error-[NCE] Non-constant expression
The following expression should be a constant.
Expression: (this.i * 12)
“…/verification/mss_uvm_tb/uvcs/brs_uvc/src/agents/rem_brs_agent/src/rem_brs_monitor.sv”,
113
Source info: file_data_re0[((i+1)12)-1 +: i12] = data_re0;
‘this’ is not an elaboration-time constant. To correct the error you may
convert this const variable to a parameter or a localparam.

10

In reply to srinivas.emb27:
You can write this as

for(i=0; i<=11;i++) begin
       file_data_re0[i*12 +: 12] = data_re0;
       file_data_im0[i*12 +: 12] = data_im0;
 end

or simply

file_data_re0 = {12{data_re0}};
file_data_im0 = {12{data_im0}};
11

In reply to dave_59:

Noorulla,
Perhaps you should explain why you need bit-slicing, and how data and temp are declared. If they are

bit [100:0] data,temp;

then the following should work

data [79:0] = temp[79:0];

Maybe you did not post your example correctly.

// hello dave in this above example if only 8 bit slicing needs for ex : [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] and so on

12

In reply to mansi m joshi:

That could be accomplished with the streaming operator

data[79:0] = {<<8(temp[79:0]}};

See section 11.4.14.2 Re-ordering of the generic stream in the 1800-2017 LRM

13

In reply to dave_59:

Hi Dave,

I have requirement like below. Can you please suggest, How can i do it?

DATA[(8 × Upper_Byte_Lane) + 7 : (8 × Lower_Byte_Lane)].

This i need for AXI.

Thanks and regards,
Piyush