Bit slicing in systemVerilog

[dave_59]

In reply to srinivas.emb27:
You can write this as

for(i=0; i<=11;i++) begin
       file_data_re0[i*12 +: 12] = data_re0;
       file_data_im0[i*12 +: 12] = data_im0;
 end

or simply

file_data_re0 = {12{data_re0}};
file_data_im0 = {12{data_im0}};