Bit slicing in systemVerilog

Hi Ajeetha,

Tried the below code for variable length part select.

reg [143:0] file_data_re0;
  reg [143:0] file_data_im0;
  
  bit [11:0] data_re0;
  bit [11:0] data_im0;
  
for(i=0; i<=11;i++) begin
       file_data_re0[((i+1)*12)-1 +: i*12] = data_re0;
       file_data_im0[((i+1)*12)-1 +: i*12] = data_im0;
 end

getting the following error
Error-[NCE] Non-constant expression
The following expression should be a constant.
Expression: (this.i * 12)
“…/verification/mss_uvm_tb/uvcs/brs_uvc/src/agents/rem_brs_agent/src/rem_brs_monitor.sv”,
113
Source info: file_data_re0[((i+1)12)-1 +: i12] = data_re0;
‘this’ is not an elaboration-time constant. To correct the error you may
convert this const variable to a parameter or a localparam.