Bit slicing in systemVerilog

In reply to MdNoorulla:

Noorulla,
Suggest you read V2K LRM on this. As you mentioned:

data[(i8)+7 : (i8)] as i varies the ranges varies from 7:0, 15:8

In this case, your slice-width is indeed a CONSTANT and not variable. Only the position is run-time variable. So the following should work:

data[(i*8)+7 -: 8]

Try and let us know if it doesn’t. Post a full code if you still see issue.

HTH
Ajeetha, CVC