Bit slicing in systemVerilog

In reply to dave_59:

Noorulla,
Perhaps you should explain why you need bit-slicing, and how data and temp are declared. If they are

bit [100:0] data,temp;

then the following should work

data [79:0] = temp[79:0];

Maybe you did not post your example correctly.

// hello dave in this above example if only 8 bit slicing needs for ex : [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] and so on