Hi,
Please help as I am confused over the following questions related to classes in System Verilog.
- What does $cast means in terms of casting classes ? Casting other types like bits to enum can be easily grasp. However, I do not understand casting classes. For example, if I cast a child class (child_) to a parent class(parent_) then what does it mean ?
- What is the difference between assignment and $cast like in the example below ?
- How does parent class handle able to view bit foo_mem which is member of child_ through function foo() ?
Sorry for my fundamental question on classes. I have to ask because IEEE System Verilog LRM 2009 does not explain the mechanism in details.
class parent_; virtual function foo_; endclass child_ extends parent_;
bit foo_mem;
function void foo_();
$display(“I am child with member of values %d”,foo_mem);
endfunction
endclass
module foo_foo;
parent_ parent_handle;
parent_ parent_handle_1;
child_ child_handle;
initial begin
child_handle = new();
$cast(parent_handle,child_handle);//
parent_handle_1 = child_handle; // What is the difference between this line and the $cast above ?
parent_handle_1.foo();
parent_handle.foo_();
end
endmodule