Confusion over casting of classes

SystemVerilog
5

In reply to rui huang:

If change the code as following it works:

class base;
   virtual function void display();
         $display(" This is base");
   endfunction
endclass

class child extends base;
   virtual function void display();
         $display(" This is sub-class");
   endfunction
 endclass
   
  program main ;
     child my_child;
     base my_base;
       
       initial
       begin
           my_child = new();
           my_base = my_child;
           my_child.display();
           my_base.display();
       end
   endprogram

The simulation result is:
This is sub-class
This is sub-class