Confusion over casting of classes

SystemVerilog
7

In reply to dave_59:

Hi,

I am getting error in Questa for the following $cast statement:


class master_read_seq extends m_transfer;
  m_transfer m_trx;
  function new(string name ="master_read_seq",
               
               int unsigned addr_delay  = 0,
               int unsigned data_delay  = 0);

    super.new(name);
    $cast(m_trx, super);

near “)”: syntax error, unexpected ‘)’, expecting ‘.’

Is it expected

Regards,
Chandan