Confusion over casting of classes

SystemVerilog
10

In reply to chandanc9:

m_trx = this;

But I don’t know why you need m_trx anyways. What you are writing would be the same as

class master_read_seq extends m_transfer;

  function new(string name ="master_read_seq",
 
               int unsigned addr_delay  = 0,
               int unsigned data_delay  = 0);
     super.new(name);
    this.addr_rd_delay = addr_delay;
    this.data_rd_delay = data_delay;