Confusion over casting of classes

SystemVerilog
9

In reply to dave_59:

Hi Dave,

Thanks for your reply. I tried using “this.m_trx” but it also did not work.
So are the following assignments correct without the $cast :


class master_read_seq extends m_transfer;
  m_transfer m_trx;
  function new(string name ="master_read_seq",
 
               int unsigned addr_delay  = 0,
               int unsigned data_delay  = 0);
     super.new(name);
    //$cast(m_trx, super);
    m_trx.addr_rd_delay = addr_delay;
    m_trx.data_rd_delay = data_delay;

Thanks and regards,
Chandan