Confusion over casting of classes

SystemVerilog
14

In reply to UVM_LOVE:

I do not like using parent/child terminology. I prefer base/derived.

$cast(dest,source);[/systemverilogThe equivalent pseudo-code for the above is

``` verilog
if (_get_type_of_handle_stored_in_(source) _is_same_or_extended_from_ _get_type_of(dest)
   dest = source
else
   $error("Incompatible type in source variable cannot be assigned to dest variable);

I think you still do not get the difference between the following concepts

  • class type
  • class handle
  • class object
  • class variable

I have explained that in great detail in A Short Class on SystemVerilog Classes - Verification Horizons and SystemVerilog OOP for UVM Verification | Track.

Maybe someone else needs to try to explain using different word.