Generate block in SV

SystemVerilog
1 
`define num =4
module enhance();
logic ssp , br ,clk , reset;
genvar i,j;

generate 
 begin:upstream
   for(i=0;i<2*`num;i++)begin
       ocp_level ocp(clk,reset);      //interface 
      assign i.data = `wrapper.signal.val;
      assign i.mdata= `wrapper.signal.read;

     if(j<`num) begin
   
       ocp_level ocp(clk,reset);      //interface 
       assign i.updata = `wrapper.signal.val;
       assign i.upmdata= `wrapper.signal.read;
      end
    j=(i/2)+1;                    ----------------1.
 end
end
endgenerate

Here I am using generate block .
case1. when both j and i is defined as genvar, than increment done in point 1 is not valid one, as we cannot update genvar inside the generate block.
or
case2 . if I take j as int than increment done in point 1 is valid but it throw error at if statement saying that it should elaboration time constant.
but cant even add initial begin becz I have interface in my code which I want it to work with generate loop.

So please suggest the way I can increment the if loop.

Thankyou.

2

In reply to shiwani chadha:

Hi shiwani,
Probably below logic would work for you.


`define num 4
module enhance();
logic ssp , br ,clk , reset;
genvar i,j;
 
generate 
 begin:upstream
   for(i=0 ;i<2*`num; i++)begin : block_for_i
     initial
       $display("DISPLAY : %0m i=%0d ",i);

     for(j= (i/2) + 1 ; j <= (i/2) + 1 ; j ++)
     begin : block_for_j
       if (j < `num)
       begin
        initial
          $display("DISPLAY : %0m j=%0d ",j);
       end
     end
   end
 end
endgenerate
endmodule
3

Hi ,

Thanks for the update about how to progress further but I am not sure that output what I need can be obtained from this.

o/p required

  1. first time run
    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

  2. 2nd time run

    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

this means i want both the loop to run together

or like this

i=0;
j=0;
i=1;
j=1;
i=2;
j=2;

4

Hi ,

Thanks for the update about how to progress further but I am not sure that output what I need can be obtained from this.

o/p required

  1. first time run
    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

  2. 2nd time run

    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

this means i want both the loop to run together

or like this

i=0;
j=0;
i=1;
j=1;
i=2;
j=2;

5

In reply to shiwani chadha:
Replace j with an expression

`define num =4
module enhance();
logic ssp , br ,clk , reset;
   for(genvar i=0;i<2*`num;i++)begin
       ocp_level ocp(clk,reset);      //interface 
      assign i.data = `wrapper.signal.val;
      assign i.mdata= `wrapper.signal.read;
 
     if( (i-1)/2+1<`num) begin
 
       ocp_level ocp(clk,reset);      //interface 
       assign i.updata = `wrapper.signal.val;
       assign i.upmdata= `wrapper.signal.read;
      end
 end

And did you mean to write ocp.data instead of i.data, etc.?

6

Hi ,

yes ocp.data instead of i.data.So both loops will work together with same increment value.

7

Hi , As u suggested I modified my code as below

`num 3;
module abc
genvar j,var,i;
generate
 begin: up
   for(j=0;j<2*`num;j++) begin:inst
      interface cond(clk,rst);
        assign cond.cmd=value;
   for(i=j;i<=j;i++)begin: block
     if(i<`num)begin
        interface cond(clk,rst);
        assign cond.cmddd=value;
    end
   end
 end
end
endgenerate

inteface xyz;
inital  begin
  for(int a=0;a<`num;a++)begin inst_val
      up.inst[a].obj=new();
   if(a<`num-`val)begin
    up.inst[a].obj_ip=new(); 
   end
 end
end


endmodule

over here at pt1 facing error [XMRE]cross module refernce resolution…how to solve this error.Tried to change the hierarchy of generate block but still facing the same issue.

8

In reply to shiwani chadha:

Here, up.inst[a] points to 1st for loop and there is no handle called ‘obj’.

Are you trying to do like this?


up.inst[a].cond.obj=new();

Where is your class handle located ?
Is it in interface ? If yes then use above syntax.

9

num 3; module abc genvar j,var,i; generate begin: up for(j=0;j<2*num;j++) begin:inst
interface cond(clk,rst);
containet #(virtual interface) obj_ds;

    assign cond.cmd=value;

for(i=j;i<=j;i++)begin: block
if(i<`num)begin
interface cond(clk,rst);
containet #(virtual interface) obj_us;
assign cond.cmddd=value;
end
end
end
end
endgenerate

inteface xyz;
inital begin
for(int a=0;a<num;a++)begin inst_val up.inst[a].obj_ds=new(); if(a<num-`val)begin
up.inst[a].obj_us=new();
end
end
end

endmodule

To be more presice please see above code . Here i am facing cross modulation error

10

In reply to shiwani chadha:

You can do like this.



`define num 3
`define val 2

interface intf();
  int a;
endinterface : intf

module abc();

class containet;

endclass : containet

genvar j,i;
generate
begin: up
  for(j=0;j<2*`num;j++) begin:inst
  containet  obj_ds;
  intf ivf();
  
    for(i=j;i<=j;i++)begin: block
      if(i<`num) begin : block_if   // Here give name to if block 
        intf ivf1();
        containet obj_us;
      end
    end
  end
end
endgenerate

genvar a;
generate 
  for(a=0;a<`num;a++)begin

    initial begin
      up.inst[a].obj_ds=new();
      if(a<`num-`val)begin
        up.inst[a].block[a].block_if.obj_us = new(); // Here , use proper hierarchical name.
      end
    end
  end
endgenerate

endmodule

Its illegal to use ‘int a’ variable for generate block array. You have to use generate block array inside generate block using genvar type.