Generate block in SV

SystemVerilog
7

Hi , As u suggested I modified my code as below

`num 3;
module abc
genvar j,var,i;
generate
 begin: up
   for(j=0;j<2*`num;j++) begin:inst
      interface cond(clk,rst);
        assign cond.cmd=value;
   for(i=j;i<=j;i++)begin: block
     if(i<`num)begin
        interface cond(clk,rst);
        assign cond.cmddd=value;
    end
   end
 end
end
endgenerate

inteface xyz;
inital  begin
  for(int a=0;a<`num;a++)begin inst_val
      up.inst[a].obj=new();
   if(a<`num-`val)begin
    up.inst[a].obj_ip=new(); 
   end
 end
end


endmodule

over here at pt1 facing error [XMRE]cross module refernce resolution…how to solve this error.Tried to change the hierarchy of generate block but still facing the same issue.