Generate block in SV

SystemVerilog
4

Hi ,

Thanks for the update about how to progress further but I am not sure that output what I need can be obtained from this.

o/p required

  1. first time run
    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

  2. 2nd time run

    assign i.data = wrapper.signal.val; assign i.mdata= wrapper.signal.read;
    //if condition
    assign i.updata = wrapper.signal.val; assign i.upmdata= wrapper.signal.read;

this means i want both the loop to run together

or like this

i=0;
j=0;
i=1;
j=1;
i=2;
j=2;