" uvm_do_on_with " constraint issue


I have problem with uvm_do_on_with…

I have seq as below…

class mem_abv_seq extends mem_base_sequence;
function new(string name="mem_abv_seq");


virtual task body();
	`uvm_info(get_type_name(),"Calling mem_abv_seq sequence",UVM_LOW)
	repeat (100) begin
		{ req.addr >= 150; req.data < 150; } )

endclass : mem_abv_seq

this sequence constraint modified from the virtual seq…

class mem_vseq extends uvm_sequence;
	mem_zero_seq mem_zero;
	mem_abv_seq mem_abv;

	function new(string name="mem_vseq");

	task body();
         `uvm_do_on_with(mem_abv,p_sequencer.memseqr,{req.addr >= 200;})

endclass : mem_vseq

There is no issue, if I use “uvm_do_on”, but issue with “uvm_do_on_with”

Getting error as below…

`uvm_do_on_with(mem_abv,p_sequencer.memseqr,{req.addr >= 200;})
ncsim: *E,RNDCNSTE (./mem_vseq.sv,44|71): Randomization constraint has this error, which will cause the randomize function to return 0 and no new rand values will be set:
Null handle references in constraints are not supported.
1030 NS + 5 (stop Randomize: Randomize failure)

What could be the issue??
How this constrains works??
Highest constraint override with lower constrains right?


Surpringly, I did not get any response on this yet…

I have same problem in hierarchical seqeunces as well.

class mem_hier_seq extends mem_base_sequence;
mem_zero_seq mem_zero;
mem_abv_seq mem_abv;
mem_blw_seq mem_blw;

virtual task body();
	`uvm_info(get_type_name(),"Calling mem_hier_seq sequence",UVM_LOW)
        `uvm_do(mem_zero) //works
	`uvm_do(mem_abv)  // works


	{req.addr == 100; req.data == 200;}) //did not work

	`uvm_info(get_type_name()," mem_hier_seq Done!!",UVM_LOW)

endclass : mem_hier_seq

somebody clarify, how we can add constraint for sequence at higher level ??


This is just another reason I prefer not to use the `uvm_do macros. Instead, you can do something like

mem_abv = mem_abv_seq::type_id::create("mem_abv");
mem_abv.randomize() with {req.addr >= 200;};

Give it a shot.

In reply to tfitz:

Thanks Tom.

I know this will work if I’m not using `uvm_do macro.

my point here is to report the `uvm_do macro issue.

interestingly, uvm_do_with macro constraint works only with local variable in seq.

Let say, I have local variable “add” in sequence which is getting assigned to req.addr with some constraint, which can able to constraint again from the higher level.

Is there going to be fix for those issues in recent times? Or uvm_macro meant for this for particular reasons?



I came through this question as i am facing the same problem.

Can you please tell me if you found any soltn to this prob, uvm_do_on_with constraint issue.

I am doing this inside the virtual function:

class mem_sequence extends base_sequence;

function new(string name="mem_sequence");

`uvm_declare_p_sequencer (abc_sequencer)

virtual task body;
`uvm_do_on_with(seq1, p_sequencer.seqr1,{ 
req.x inside [0,1,3,4];
req.y inside [2,6];


Am wwhat i am doing is valid ?
Please guide me if this can be done .

In reply to tfitz:
Hi Tom,
I use the method you suggested, in my sequence, I a child sequence, I create/start it as below

        ts_mb_seq = ts_mb_base_sequence_c::type_id::create("ts_mb_seq");
        ts_mb_seq.randomize() with {req.crc24_error == FALSE;};

I got a run time randomization error with ncsim because of a Null ptr reference.
I understand that at this point, the req of the ts_mb_seq isn’t created yet. How can I get around this, or is this just a ncsim specific issue?
The error below. Thanks.

        ts_mb_seq.randomize() with {req.crc24_error == FALSE;};

ncsim: *E,RNDCNSTE (…/uvcs/plc_gen_uvc/src/sequences/plc_base_sequence.sv,110|42): Randomization constraint has this error, which will cause the randomize function to return 0 and no new rand values will be set:
Null handle references in constraints are not supported.
27670 NS + 29 (stop Randomize: Randomize failure)

In reply to hah:

You get this randomization error, because you did not construct req.
And you are mixing 2 different seq_items.

The correct syntax for the macro is

`uvm_do_with(req, {addr >= 150; data < 150; } )

where addr and data are members of your seq_item.

In reply to hah:

The general issue here is you have a pair of layered/hierarchical sequences, and you are trying to randomize both the lower level sequence and sequence_item at the same time before the sequence_item (req) gets constructed. There are several approaches to solving this problem.

The reccomended OOP way of doing this is avoiding using the
clause, which is not OOP friendly. Instead, use the factory to override whatever sequence_item class gets created by the lower level sequence with an extended class that adds the constraint you want.

In reply to dave_59:
Hi Dave,

Can you help me, that what is wrong here

Basically this is my pkt and I want to assign 0 value to a particular field according to ln_align_lost.

  task ln_align_lost_fmt(bit [1:0] slice_idx, comlink_id);
    bit [31:0] ln_align_lost;
                        { dll_frame_typ   == NORMAL;
                          if(cla.is_present("-rx_ln_align_lost"))begin // this is command line switch, if I give it then only I want to assign value
                            ln_align_lost = $urandom_range(1,8);
                            if(ln_align_lost == 1)begin
                              fc1 = 0;
                            end else if(ln_align_lost == 2)begin
                              fc0 = 0;  
                            end else if(ln_align_lost == 3)begin
                              ack_id = 0; 
                            end else if(ln_align_lost == 4)begin
                              ack_valid = 0;
                            end else if(ln_align_lost == 5)begin
                              pkt_id = 0; 
                            end else if(ln_align_lost == 6)begin
                              irp_pkt_typ = 0;
                            end else if(ln_align_lost == 7)begin
                              eop = 0;  
                            end else if(ln_align_lost == 8)begin
                              sop = 0; 
                   ) // Getting error here

I am getting this error “illegal expression primary [4.2(IEEE)].)”

In reply to J_M:

Remember that a constraint is not procedure code, it’s just a big equation. So no begin/end or assignments.